<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23785">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/romstage.c: Fix AGESA warning<br><br>AmdInitPost returns AGESA_WARNING. This is because AGESA by default<br>enables bank interleaving, while the HW does not meet the requirements<br>for it. After some investigation, it was found that AGESA was really<br>checking rank.<br><br>In preparation to control interleaving, create a function that returns<br>the number of ranks for DDR3 and DDR4.<br><br>BUG=b:73118857<br>TEST= Build and run kahlee. Use a print over serial to display DDR3/DDR4<br>and the number of ranks. Remove the print before committing.<br><br>Change-Id: I002328d1029c968c371ff751986537135231f306<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/romstage.c<br>1 file changed, 33 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/23785/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 490fd9e..351a266 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -31,6 +31,7 @@</span><br><span> #include <soc/northbridge.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <amdblocks/psp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <amdblocks/dimm_spd.h></span><br><span> </span><br><span> asmlinkage void car_stage_entry(void)</span><br><span> {</span><br><span>@@ -130,6 +131,36 @@</span><br><span> post_code(0x50); /* Should never see this post code. */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t get_total_ranks(const struct soc_amd_stoneyridge_config *cfg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t err, spd_address, ranks, spd_rank, type, spd[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_address = cfg->spd_addr_lookup[0][0][0];</span><br><span style="color: hsl(120, 100%, 40%);">+ err = mainboard_read_spd(spd_address, (void *)spd, 16);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read the SPD if the mainboard didn't fill the buffer */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (err || (*spd == 0))</span><br><span style="color: hsl(120, 100%, 40%);">+ err = sb_read_spd(spd_address, (void *)spd, 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (err)</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1; /* for safety, just 1 rank */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ type = spd[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x0b:</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_rank = spd[7]; /* DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x0c:</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_rank = spd[12]; /* DDR4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_rank = 0; /* will force 1 rank */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_rank &= 0x38; /* rank mask for DDR3 and DDR4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ ranks = spd_rank >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranks++;</span><br><span style="color: hsl(120, 100%, 40%);">+ return ranks;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void SetMemParams(AMD_POST_PARAMS *PostParams)</span><br><span> {</span><br><span> const struct soc_amd_stoneyridge_config *cfg;</span><br><span>@@ -144,6 +175,8 @@</span><br><span> }</span><br><span> </span><br><span> cfg = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t ranks = get_total_ranks(cfg);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "Ranks %d\n", ranks);</span><br><span> </span><br><span> PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23785">change 23785</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I002328d1029c968c371ff751986537135231f306 </div>
<div style="display:none"> Gerrit-Change-Number: 23785 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>