<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23777">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Make proper use of addressmap.h<br><br>Removed hardcoded addresses and use addressmap.h instead.<br><br>Change-Id: I5f0463eb202fb45ec3c2340c4389028758de688a<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/soc/cavium/cn81xx/Kconfig<br>M src/soc/cavium/cn81xx/Makefile.inc<br>M src/soc/cavium/cn81xx/bootblock_custom.S<br>M src/soc/cavium/cn81xx/include/soc/addressmap.h<br>M src/soc/cavium/cn81xx/include/soc/memlayout.ld<br>D src/soc/cavium/cn81xx/twsi.c<br>M src/soc/cavium/common/clock.c<br>M src/soc/cavium/common/gpio.c<br>M src/soc/cavium/common/include/soc/twsi.h<br>M src/soc/cavium/common/twsi.c<br>10 files changed, 72 insertions(+), 92 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23777/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig</span><br><span>index 914bcf7..0693033 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Kconfig</span><br><span>+++ b/src/soc/cavium/cn81xx/Kconfig</span><br><span>@@ -30,11 +30,6 @@</span><br><span> # select VBOOT_OPROM_MATTERS</span><br><span> # select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-# Address the BOOTROM loads the bootblock to</span><br><span style="color: hsl(0, 100%, 40%);">-config BOOTROM_OFFSET</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x100000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config PMIC_BUS</span><br><span> int</span><br><span> default -1</span><br><span>diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>index 91d71dd..c16c378 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>+++ b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>@@ -27,13 +27,10 @@</span><br><span> #bootblock-y += ../common/pwm.c</span><br><span> bootblock-y += bootblock.c</span><br><span> #bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += twsi.c</span><br><span> bootblock-y += l2c.c</span><br><span> bootblock-y += mmu_operations.c</span><br><span> #bootblock-y += sdram.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += twsi.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> romstage-y += sdram.c</span><br><span> romstage-y += ../common/bdk/libdram/libdram.c</span><br><span> romstage-y += ../common/bdk/libbdk-arch/bdk-csr.c</span><br><span>@@ -92,7 +89,6 @@</span><br><span> ramstage-y += ../common/cbmem.c</span><br><span> ramstage-y += sdram.c</span><br><span> ramstage-y += spi.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += twsi.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> #ramstage-y += ../common/gpio.c</span><br><span> #ramstage-y += gpio.c</span><br><span>diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>index fab2e43..69985b7 100644</span><br><span>--- a/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>+++ b/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>@@ -16,6 +16,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/asm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span> </span><br><span> ENTRY(_start)</span><br><span> .org 0</span><br><span>@@ -50,19 +51,15 @@</span><br><span> #error Unknown endianness</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- #define BDK_LMCX 0x87e088000000ULL</span><br><span style="color: hsl(0, 100%, 40%);">- #define DDR_PLL_CTL0 0x258</span><br><span style="color: hsl(0, 100%, 40%);">- mov x0, (BDK_LMCX >> 32)</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x0, (LMC0_PF_BAR0 >> 32)</span><br><span> lsl x0, x0, 32</span><br><span style="color: hsl(0, 100%, 40%);">- mov x1, (BDK_LMCX & 0xffffffff)</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x1, (LMC0_PF_BAR0 & 0xffffffff)</span><br><span> orr x0, x0, x1</span><br><span> </span><br><span> /* Test if DRAM PLL is running */</span><br><span style="color: hsl(0, 100%, 40%);">- ldr x1, [x0, DDR_PLL_CTL0]</span><br><span style="color: hsl(120, 100%, 40%);">+ ldr x1, [x0, LMC0_DDR_PLL_CTL0]</span><br><span> </span><br><span> tst x1, 0x80</span><br><span style="color: hsl(0, 100%, 40%);">- #undef BDK_LMCX</span><br><span style="color: hsl(0, 100%, 40%);">- #undef DDR_PLL_CTL0</span><br><span> </span><br><span> b.ne cache_setup_done</span><br><span> </span><br><span>@@ -81,7 +78,7 @@</span><br><span> node_check_done:</span><br><span> /* Get code position */</span><br><span> mov x1, 0x020000</span><br><span style="color: hsl(0, 100%, 40%);">- mov x0, CONFIG_BOOTROM_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x0, BOOTROM_OFFSET</span><br><span> add x1, x0, x1</span><br><span> </span><br><span> adr x0, _start</span><br><span>@@ -114,7 +111,7 @@</span><br><span> adr x0, after_relocate /* Relative address */</span><br><span> adr x1, _start /* Relative address */</span><br><span> sub x0, x0, x1 /* This only works if _start is suppose to be zero */</span><br><span style="color: hsl(0, 100%, 40%);">- mov x1, CONFIG_BOOTROM_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x1, BOOTROM_OFFSET</span><br><span> add x0, x0, x1</span><br><span> br x0 /* Branch to relocated code */</span><br><span> </span><br><span>@@ -148,13 +145,12 @@</span><br><span> * - CN83XX</span><br><span> * - CN88XX</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- #define L2C_ASC_REGIONX 0x87E080800000</span><br><span> #define REGIONX_START 0x1000</span><br><span> #define REGIONX_END 0x1008</span><br><span> #define REGIONX_ATTR 0x1010</span><br><span style="color: hsl(0, 100%, 40%);">- mov x0, L2C_ASC_REGIONX >> 32</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x0, L2C_PF_BAR0 >> 32</span><br><span> lsl x0, x0, 32</span><br><span style="color: hsl(0, 100%, 40%);">- mov x1, (L2C_ASC_REGIONX & 0xffffffff)</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x1, (L2C_PF_BAR0 & 0xffffffff)</span><br><span> orr x0, x0, x1</span><br><span> str xzr, [x0, REGIONX_START] /* Start of zero */</span><br><span> mov x1, 0x3fffff00000 /* End of max address */</span><br><span>@@ -168,7 +164,6 @@</span><br><span> mov x1, L2C_WPAR_PP0_OFFSET</span><br><span> str xzr, [x0, x1]</span><br><span> ldr xzr, [x0, x1] /* Read back to make sure done */</span><br><span style="color: hsl(0, 100%, 40%);">- #undef L2C_ASC_REGIONX</span><br><span> #undef REGIONX_START</span><br><span> #undef REGIONX_END</span><br><span> #undef REGIONX_ATTR</span><br><span>@@ -233,12 +228,10 @@</span><br><span> * address space, some interrupt flags had been set.</span><br><span> * Tidy up our mess now on (valid for CN81XX only).</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- #define L2C_TAD0_INT_W1C 0x87e050040000ULL</span><br><span> mov x0, (L2C_TAD0_INT_W1C >> 32)</span><br><span> lsl x0, x0, 32</span><br><span> mov x1, (L2C_TAD0_INT_W1C & 0xffffffff)</span><br><span> orr x0, x0, x1</span><br><span style="color: hsl(0, 100%, 40%);">- #undef L2C_TAD0_INT_W1C</span><br><span> </span><br><span> ldr x1, [x0]</span><br><span> orr x1, x1, 0x1c00 /* Clear WRDISLMC, RDDISLMC, RDNXM */</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h</span><br><span>index 01fd6ae..e235494 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/addressmap.h</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h</span><br><span>@@ -16,86 +16,100 @@</span><br><span> #ifndef __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__</span><br><span> #define __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_DRAM_ADDRESS 0x2000000000 /* 128GB */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_DRAM_ADDRESS 0x2000000000ULL /* 128GB */</span><br><span> </span><br><span> /* Physical addressed with bit 47 set indicate I/O memory space. */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* ARM code entry vector */</span><br><span style="color: hsl(120, 100%, 40%);">+#define BOOTROM_OFFSET 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* L2C */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L2C_PF_BAR0 0x87E080800000</span><br><span style="color: hsl(0, 100%, 40%);">-#define L2C_TAD0_PF_BAR0 (0x87E050000000 + 0x10000)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L2C_CBC0_PF_BAR0 0x87E058000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define L2C_MCI0_PF_BAR0 0x87E05C000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_PF_BAR0 0x87E080800000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD0_PF_BAR0 (0x87E050000000ULL + 0x10000)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD0_INT_W1C (0x87E050000000ULL + 0x40000)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_CBC0_PF_BAR0 0x87E058000000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_MCI0_PF_BAR0 0x87E05C000000ULL</span><br><span> </span><br><span> /* LMC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define LMC0_PF_BAR0 0x87E088000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define LMC0_PF_BAR0 0x87E088000000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+#define LMC0_DDR_PLL_CTL0 0x258</span><br><span> </span><br><span> /* OCLA */</span><br><span> </span><br><span> /* IOB */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOBN0_PF_BAR0 0x87E0F0000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define MRML_PF_BAR0 0x87E0FC000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOBN0_PF_BAR0 0x87E0F0000000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRML_PF_BAR0 0x87E0FC000000ULL</span><br><span> </span><br><span> /* SMMU */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMMU_PF_BAR0 0x830000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMMU_PF_BAR0 0x830000000000ULL</span><br><span> </span><br><span> /* GTI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GTI_PF_BAR0 0x844000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GTI_PF_BAR0 0x844000000000ULL</span><br><span> </span><br><span> /* PCC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ECAM_PF_BAR2 0x848000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define ECAM_PF_BAR2 0x848000000000ULL</span><br><span> </span><br><span> /* CPT */</span><br><span> /* SLI */</span><br><span> </span><br><span> /* RST */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_PF_BAR0 (0x87E006000000 + 0x1600)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FUSF_PF_BAR0 0x87E004000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIO_FUS_PF_BAR0 0x87E003000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIO_BOOT_PF_BAR0 0x87E000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define RST_PF_BAR0 (0x87E006000000ULL + 0x1600)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FUSF_PF_BAR0 0x87E004000000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIO_FUS_PF_BAR0 0x87E003000000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIO_BOOT_PF_BAR0 0x87E000000000ULL</span><br><span> </span><br><span> /* PTP */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIO_PTP_PF_BAR0 0x807000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIO_PTP_PF_BAR0 0x807000000000ULL</span><br><span> </span><br><span> /* GIC */</span><br><span> /* NIC */</span><br><span> /* LBK */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GTI_PF_BAR0 0x844000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GTI_PF_BAR0 0x844000000000ULL</span><br><span> </span><br><span> /* DAP */</span><br><span> /* BCH */</span><br><span> /* KEY */</span><br><span> /* RNG */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GSER0_PF_BAR0 (0x87E090000000 + (0 << 24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GSER1_PF_BAR0 (0x87E090000000 + (1 << 24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GSER2_PF_BAR0 (0x87E090000000 + (2 << 24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define GSER3_PF_BAR0 (0x87E090000000 + (3 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSER0_PF_BAR0 (0x87E090000000ULL + (0 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSER1_PF_BAR0 (0x87E090000000ULL + (1 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSER2_PF_BAR0 (0x87E090000000ULL + (2 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSER3_PF_BAR0 (0x87E090000000ULL + (3 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSERx_PF_BAR0(x) \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x87E090000000ULL + ((x) << 24)) : 0)</span><br><span> </span><br><span> /* PEM */</span><br><span> /* SATA */</span><br><span> /* USB */</span><br><span> </span><br><span> /* UAA */</span><br><span style="color: hsl(0, 100%, 40%);">-#define UAA0_PF_BAR0 (0x87E028000000 + (0 << 24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define UAA1_PF_BAR0 (0x87E028000000 + (1 << 24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define UAA2_PF_BAR0 (0x87E028000000 + (2 << 24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define UAA3_PF_BAR0 (0x87E028000000 + (3 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define UAA0_PF_BAR0 (0x87E028000000ULL + (0 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define UAA1_PF_BAR0 (0x87E028000000ULL + (1 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define UAA2_PF_BAR0 (0x87E028000000ULL + (2 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define UAA3_PF_BAR0 (0x87E028000000ULL + (3 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define UAAx_PF_BAR0(x) \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x87E028000000ULL + ((x) << 24)) : 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> /* TWSI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIO_TWS0_PF_BAR0 (0x87E0D0000000 + (0 << 24))</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIO_TWS1_PF_BAR0 (0x87E0D0000000 + (1 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIO_TWS0_PF_BAR0 (0x87E0D0000000ULL + (0 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIO_TWS1_PF_BAR0 (0x87E0D0000000ULL + (1 << 24))</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIO_TWSx_PF_BAR0(x) \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((((x) == 0) || ((x) == 1)) ? (0x87E0D0000000ULL + ((x) << 24)) : 0)</span><br><span> </span><br><span> /* GPIO */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_PF_BAR0 0x803000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PF_BAR0 0x803000000000ULL</span><br><span> </span><br><span> /* SGPIO */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SGP_PF_BAR0 0x803000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SGP_PF_BAR0 0x803000000000ULL</span><br><span> </span><br><span> /* SMI */</span><br><span> </span><br><span> /* SPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MPI_PF_BAR0 (0x804000000000 + 0x1000)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MPI_PF_BAR0 (0x804000000000ULL + 0x1000)</span><br><span> </span><br><span> /* PCM */</span><br><span> /* PBUS */</span><br><span>@@ -104,6 +118,6 @@</span><br><span> </span><br><span> /* VRM */</span><br><span> /* VRM BARs are spaced apart by 0x1000000 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VRM0_PF_BAR0 0x87E021000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define VRM0_PF_BAR0 0x87E021000000ULL</span><br><span> </span><br><span> #endif /* __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ */</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>index 42e62e4..949702d 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <memlayout.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span> #include <arch/header.ld></span><br><span> </span><br><span> SECTIONS</span><br><span>@@ -37,17 +38,17 @@</span><br><span> */ </span><br><span> </span><br><span> /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */</span><br><span style="color: hsl(0, 100%, 40%);">- SRAM_START(CONFIG_BOOTROM_OFFSET)</span><br><span style="color: hsl(0, 100%, 40%);">- STACK(CONFIG_BOOTROM_OFFSET, 16K)</span><br><span style="color: hsl(120, 100%, 40%);">+ SRAM_START(BOOTROM_OFFSET)</span><br><span style="color: hsl(120, 100%, 40%);">+ STACK(BOOTROM_OFFSET, 16K)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- PRERAM_CBFS_CACHE(CONFIG_BOOTROM_OFFSET + 0x4000, 8K)</span><br><span style="color: hsl(0, 100%, 40%);">- TIMESTAMP(CONFIG_BOOTROM_OFFSET + 0x6000, 2K)</span><br><span style="color: hsl(0, 100%, 40%);">- PRERAM_CBMEM_CONSOLE(CONFIG_BOOTROM_OFFSET + 0x8000, 8K)</span><br><span style="color: hsl(120, 100%, 40%);">+ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x4000, 8K)</span><br><span style="color: hsl(120, 100%, 40%);">+ TIMESTAMP(BOOTROM_OFFSET + 0x6000, 2K)</span><br><span style="color: hsl(120, 100%, 40%);">+ PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- BOOTBLOCK(CONFIG_BOOTROM_OFFSET + 0x20000, 64K)</span><br><span style="color: hsl(0, 100%, 40%);">- TTB(CONFIG_BOOTROM_OFFSET + 0x30000, 64K)</span><br><span style="color: hsl(0, 100%, 40%);">- ROMSTAGE(CONFIG_BOOTROM_OFFSET + 0x40000, 256K)</span><br><span style="color: hsl(0, 100%, 40%);">- SRAM_END(CONFIG_BOOTROM_OFFSET + 0x80000)</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)</span><br><span style="color: hsl(120, 100%, 40%);">+ TTB(BOOTROM_OFFSET + 0x30000, 64K)</span><br><span style="color: hsl(120, 100%, 40%);">+ ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)</span><br><span style="color: hsl(120, 100%, 40%);">+ SRAM_END(BOOTROM_OFFSET + 0x80000)</span><br><span> </span><br><span> POSTRAM_CBFS_CACHE(0x2000000, 1M)</span><br><span> RAMSTAGE(0x3000000, 256K)</span><br><span>diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c</span><br><span>deleted file mode 100644</span><br><span>index a87de79..0000000</span><br><span>--- a/src/soc/cavium/cn81xx/twsi.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,20 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2018-present Facebook, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * SPDX-License-Identifier: GPL-2.0+</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <stddef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <assert.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/twsi.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void *const twsi_bus[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- (void *const)0x87E0D0000000ULL,</span><br><span style="color: hsl(0, 100%, 40%);">- (void *const)0x87E0D1000000ULL,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void *twsi_get_baseaddr(const size_t bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- assert (bus < ARRAY_SIZE(twsi_bus));</span><br><span style="color: hsl(0, 100%, 40%);">- if (bus >= ARRAY_SIZE(twsi_bus))</span><br><span style="color: hsl(0, 100%, 40%);">- return NULL;</span><br><span style="color: hsl(0, 100%, 40%);">- return twsi_bus[bus];</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/cavium/common/clock.c b/src/soc/cavium/common/clock.c</span><br><span>index 1a5664d..14ab58a 100644</span><br><span>--- a/src/soc/cavium/common/clock.c</span><br><span>+++ b/src/soc/cavium/common/clock.c</span><br><span>@@ -7,8 +7,8 @@</span><br><span> */</span><br><span> #include <soc/clock.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT ((void *const)0x87e006001600ll)</span><br><span> #define PLL_REF_CLK 50000000 /* 50 MHz */</span><br><span> </span><br><span> union cavm_rst_boot {</span><br><span>@@ -53,7 +53,7 @@</span><br><span> {</span><br><span> union cavm_rst_boot rst_boot;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- rst_boot.u = read64(RST_BOOT);</span><br><span style="color: hsl(120, 100%, 40%);">+ rst_boot.u = read64((void *)RST_PF_BAR0);</span><br><span> </span><br><span> return rst_boot.s.pnr_mul * PLL_REF_CLK;</span><br><span> }</span><br><span>@@ -65,7 +65,7 @@</span><br><span> {</span><br><span> union cavm_rst_boot rst_boot;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- rst_boot.u = read64(RST_BOOT);</span><br><span style="color: hsl(120, 100%, 40%);">+ rst_boot.u = read64((void *)RST_PF_BAR0);</span><br><span> </span><br><span> return rst_boot.s.c_mul * PLL_REF_CLK;</span><br><span> }</span><br><span>diff --git a/src/soc/cavium/common/gpio.c b/src/soc/cavium/common/gpio.c</span><br><span>index b7620e5..222ecdd 100644</span><br><span>--- a/src/soc/cavium/common/gpio.c</span><br><span>+++ b/src/soc/cavium/common/gpio.c</span><br><span>@@ -8,6 +8,7 @@</span><br><span> #include <soc/gpio.h></span><br><span> #include <arch/io.h></span><br><span> #include <endian.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span> </span><br><span> union gpio_const {</span><br><span> u64 u;</span><br><span>@@ -47,9 +48,9 @@</span><br><span> };</span><br><span> </span><br><span> /* Base address of GPIO BAR */</span><br><span style="color: hsl(0, 100%, 40%);">-static void *gpio_get_baseaddr(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static const void *gpio_get_baseaddr(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return (void *)0x803000000000ULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (const void *)GPIO_PF_BAR0;</span><br><span> }</span><br><span> </span><br><span> /* Number of GPIO pins. Usually 48. */</span><br><span>diff --git a/src/soc/cavium/common/include/soc/twsi.h b/src/soc/cavium/common/include/soc/twsi.h</span><br><span>index a9f23ad..f5c1f45 100644</span><br><span>--- a/src/soc/cavium/common/include/soc/twsi.h</span><br><span>+++ b/src/soc/cavium/common/include/soc/twsi.h</span><br><span>@@ -9,6 +9,5 @@</span><br><span> #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_TWSI_H</span><br><span> </span><br><span> int twsi_init(unsigned int bus, enum i2c_speed hz);</span><br><span style="color: hsl(0, 100%, 40%);">-void *twsi_get_baseaddr(const size_t bus);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/cavium/common/twsi.c b/src/soc/cavium/common/twsi.c</span><br><span>index d9fd3fb..e6254ee 100644</span><br><span>--- a/src/soc/cavium/common/twsi.c</span><br><span>+++ b/src/soc/cavium/common/twsi.c</span><br><span>@@ -12,6 +12,7 @@</span><br><span> #include <assert.h></span><br><span> #include <delay.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span> </span><br><span> #define TWSI_THP 24</span><br><span> </span><br><span>@@ -644,7 +645,7 @@</span><br><span> </span><br><span> int twsi_init(unsigned int bus, enum i2c_speed hz)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- void *baseaddr = twsi_get_baseaddr(bus);</span><br><span style="color: hsl(120, 100%, 40%);">+ void *baseaddr = (void *)MIO_TWSx_PF_BAR0(bus);</span><br><span> if (!baseaddr)</span><br><span> return -1;</span><br><span> </span><br><span>@@ -661,7 +662,7 @@</span><br><span> int seg_count)</span><br><span> {</span><br><span> int result;</span><br><span style="color: hsl(0, 100%, 40%);">- void *baseaddr = twsi_get_baseaddr(bus);</span><br><span style="color: hsl(120, 100%, 40%);">+ void *baseaddr = (void *)MIO_TWSx_PF_BAR0(bus);</span><br><span> if (!baseaddr)</span><br><span> return -1;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23777">change 23777</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23777"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5f0463eb202fb45ec3c2340c4389028758de688a </div>
<div style="display:none"> Gerrit-Change-Number: 23777 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>