<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23773">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">arch/riscv: Update encoding.h and adjust related code<br><br>Update encoding.h to the version shipped with spike commit<br>0185d36 ("Merge pull request #165 from riscv/small_progbuf"),<br>and copy the license header from the LICENSE file.<br><br>Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/arch/riscv/include/arch/encoding.h<br>M src/arch/riscv/trap_handler.c<br>M src/arch/riscv/virtual_memory.c<br>3 files changed, 238 insertions(+), 83 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/23773/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h</span><br><span>index 5142a78..f84c9d4 100644</span><br><span>--- a/src/arch/riscv/include/arch/encoding.h</span><br><span>+++ b/src/arch/riscv/include/arch/encoding.h</span><br><span>@@ -1,6 +1,6 @@</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2016, The Regents of the University of California (Regents).</span><br><span style="color: hsl(0, 100%, 40%);">- * All Rights Reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2010-2017, The Regents of the University of California</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Regents). All Rights Reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span> * modification, are permitted provided that the following conditions are met:</span><br><span>@@ -42,17 +42,16 @@</span><br><span> #define MSTATUS_FS 0x00006000</span><br><span> #define MSTATUS_XS 0x00018000</span><br><span> #define MSTATUS_MPRV 0x00020000</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSTATUS_PUM 0x00040000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSTATUS_SUM 0x00040000</span><br><span> #define MSTATUS_MXR 0x00080000</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSTATUS_VM 0x1F000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSTATUS_TVM 0x00100000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSTATUS_TW 0x00200000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSTATUS_TSR 0x00400000</span><br><span> #define MSTATUS32_SD 0x80000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSTATUS_UXL 0x0000000300000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSTATUS_SXL 0x0000000C00000000</span><br><span> #define MSTATUS64_SD 0x8000000000000000</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MIE_UTIE 0x00000010</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIE_STIE 0x00000020</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIE_HTIE 0x00000040</span><br><span style="color: hsl(0, 100%, 40%);">-#define MIE_MTIE 0x00000080</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define SSTATUS_UIE 0x00000001</span><br><span> #define SSTATUS_SIE 0x00000002</span><br><span> #define SSTATUS_UPIE 0x00000010</span><br><span>@@ -60,8 +59,10 @@</span><br><span> #define SSTATUS_SPP 0x00000100</span><br><span> #define SSTATUS_FS 0x00006000</span><br><span> #define SSTATUS_XS 0x00018000</span><br><span style="color: hsl(0, 100%, 40%);">-#define SSTATUS_PUM 0x00040000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSTATUS_SUM 0x00040000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSTATUS_MXR 0x00080000</span><br><span> #define SSTATUS32_SD 0x80000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SSTATUS_UXL 0x0000000300000000</span><br><span> #define SSTATUS64_SD 0x8000000000000000</span><br><span> </span><br><span> #define DCSR_XDEBUGVER (3U<<30)</span><br><span>@@ -131,19 +132,36 @@</span><br><span> </span><br><span> #define SIP_SSIP MIP_SSIP</span><br><span> #define SIP_STIP MIP_STIP</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIE_STIE MIE_STIE</span><br><span> </span><br><span> #define PRV_U 0</span><br><span> #define PRV_S 1</span><br><span> #define PRV_H 2</span><br><span> #define PRV_M 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define VM_MBARE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define VM_MBB 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define VM_MBBID 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define VM_SV32 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define VM_SV39 9</span><br><span style="color: hsl(0, 100%, 40%);">-#define VM_SV48 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP32_MODE 0x80000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP32_ASID 0x7FC00000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP32_PPN 0x003FFFFF</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP64_MODE 0xF000000000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP64_ASID 0x0FFFF00000000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP64_PPN 0x00000FFFFFFFFFFF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP_MODE_OFF 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP_MODE_SV32 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP_MODE_SV39 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP_MODE_SV48 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP_MODE_SV57 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATP_MODE_SV64 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_R 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_W 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_X 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_A 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_L 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_SHIFT 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_TOR 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_NA4 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMP_NAPOT 0x18</span><br><span> </span><br><span> #define IRQ_S_SOFT 1</span><br><span> #define IRQ_H_SOFT 2</span><br><span>@@ -158,9 +176,8 @@</span><br><span> #define IRQ_HOST 13</span><br><span> </span><br><span> #define DEFAULT_RSTVEC 0x00001000</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_NMIVEC 0x00001004</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_MTVEC 0x00001010</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONFIG_STRING_ADDR 0x0000100C</span><br><span style="color: hsl(120, 100%, 40%);">+#define CLINT_BASE 0x02000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CLINT_SIZE 0x000c0000</span><br><span> #define EXT_IO_BASE 0x40000000</span><br><span> #define DRAM_BASE 0x80000000</span><br><span> </span><br><span>@@ -181,14 +198,16 @@</span><br><span> </span><br><span> #ifdef __riscv</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef __riscv64</span><br><span style="color: hsl(120, 100%, 40%);">+#if __riscv_xlen == 64</span><br><span> # define MSTATUS_SD MSTATUS64_SD</span><br><span> # define SSTATUS_SD SSTATUS64_SD</span><br><span> # define RISCV_PGLEVEL_BITS 9</span><br><span style="color: hsl(120, 100%, 40%);">+# define SATP_MODE SATP64_MODE</span><br><span> #else</span><br><span> # define MSTATUS_SD MSTATUS32_SD</span><br><span> # define SSTATUS_SD SSTATUS32_SD</span><br><span> # define RISCV_PGLEVEL_BITS 10</span><br><span style="color: hsl(120, 100%, 40%);">+# define SATP_MODE SATP32_MODE</span><br><span> #endif</span><br><span> #define RISCV_PGSHIFT 12</span><br><span> #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)</span><br><span>@@ -198,35 +217,23 @@</span><br><span> #ifdef __GNUC__</span><br><span> </span><br><span> #define read_csr(reg) ({ unsigned long __tmp; \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \</span><br><span style="color: hsl(0, 100%, 40%);">- __tmp; })</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \</span><br><span style="color: hsl(120, 100%, 40%);">+ __tmp; })</span><br><span> </span><br><span> #define write_csr(reg, val) ({ \</span><br><span style="color: hsl(0, 100%, 40%);">- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrw " #reg ", %0" :: "i"(val)); \</span><br><span style="color: hsl(0, 100%, 40%);">- else \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrw " #reg ", %0" :: "r"(val)); })</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })</span><br><span> </span><br><span> #define swap_csr(reg, val) ({ unsigned long __tmp; \</span><br><span style="color: hsl(0, 100%, 40%);">- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \</span><br><span style="color: hsl(0, 100%, 40%);">- else \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \</span><br><span style="color: hsl(0, 100%, 40%);">- __tmp; })</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \</span><br><span style="color: hsl(120, 100%, 40%);">+ __tmp; })</span><br><span> </span><br><span> #define set_csr(reg, bit) ({ unsigned long __tmp; \</span><br><span style="color: hsl(0, 100%, 40%);">- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \</span><br><span style="color: hsl(0, 100%, 40%);">- else \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \</span><br><span style="color: hsl(0, 100%, 40%);">- __tmp; })</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \</span><br><span style="color: hsl(120, 100%, 40%);">+ __tmp; })</span><br><span> </span><br><span> #define clear_csr(reg, bit) ({ unsigned long __tmp; \</span><br><span style="color: hsl(0, 100%, 40%);">- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \</span><br><span style="color: hsl(0, 100%, 40%);">- else \</span><br><span style="color: hsl(0, 100%, 40%);">- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \</span><br><span style="color: hsl(0, 100%, 40%);">- __tmp; })</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \</span><br><span style="color: hsl(120, 100%, 40%);">+ __tmp; })</span><br><span> </span><br><span> #define rdtime() read_csr(time)</span><br><span> #define rdcycle() read_csr(cycle)</span><br><span>@@ -239,7 +246,7 @@</span><br><span> #endif</span><br><span> </span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-/* Automatically generated by parse-opcodes */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Automatically generated by parse-opcodes. */</span><br><span> #ifndef RISCV_ENCODING_H</span><br><span> #define RISCV_ENCODING_H</span><br><span> #define MATCH_BEQ 0x63</span><br><span>@@ -422,14 +429,12 @@</span><br><span> #define MASK_URET 0xffffffff</span><br><span> #define MATCH_SRET 0x10200073</span><br><span> #define MASK_SRET 0xffffffff</span><br><span style="color: hsl(0, 100%, 40%);">-#define MATCH_HRET 0x20200073</span><br><span style="color: hsl(0, 100%, 40%);">-#define MASK_HRET 0xffffffff</span><br><span> #define MATCH_MRET 0x30200073</span><br><span> #define MASK_MRET 0xffffffff</span><br><span> #define MATCH_DRET 0x7b200073</span><br><span> #define MASK_DRET 0xffffffff</span><br><span style="color: hsl(0, 100%, 40%);">-#define MATCH_SFENCE_VM 0x10400073</span><br><span style="color: hsl(0, 100%, 40%);">-#define MASK_SFENCE_VM 0xfff07fff</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_SFENCE_VMA 0x12000073</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_SFENCE_VMA 0xfe007fff</span><br><span> #define MATCH_WFI 0x10500073</span><br><span> #define MASK_WFI 0xffffffff</span><br><span> #define MATCH_CSRRW 0x1073</span><br><span>@@ -488,6 +493,34 @@</span><br><span> #define MASK_FCVT_D_S 0xfff0007f</span><br><span> #define MATCH_FSQRT_D 0x5a000053</span><br><span> #define MASK_FSQRT_D 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FADD_Q 0x6000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FADD_Q 0xfe00007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FSUB_Q 0xe000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FSUB_Q 0xfe00007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMUL_Q 0x16000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMUL_Q 0xfe00007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FDIV_Q 0x1e000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FDIV_Q 0xfe00007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FSGNJ_Q 0x26000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FSGNJ_Q 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FSGNJN_Q 0x26001053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FSGNJN_Q 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FSGNJX_Q 0x26002053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FSGNJX_Q 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMIN_Q 0x2e000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMIN_Q 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMAX_Q 0x2e001053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMAX_Q 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_S_Q 0x40300053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_S_Q 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_Q_S 0x46000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_Q_S 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_D_Q 0x42300053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_D_Q 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_Q_D 0x46100053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_Q_D 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FSQRT_Q 0x5e000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FSQRT_Q 0xfff0007f</span><br><span> #define MATCH_FLE_S 0xa0000053</span><br><span> #define MASK_FLE_S 0xfe00707f</span><br><span> #define MATCH_FLT_S 0xa0001053</span><br><span>@@ -500,6 +533,12 @@</span><br><span> #define MASK_FLT_D 0xfe00707f</span><br><span> #define MATCH_FEQ_D 0xa2002053</span><br><span> #define MASK_FEQ_D 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FLE_Q 0xa6000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FLE_Q 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FLT_Q 0xa6001053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FLT_Q 0xfe00707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FEQ_Q 0xa6002053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FEQ_Q 0xfe00707f</span><br><span> #define MATCH_FCVT_W_S 0xc0000053</span><br><span> #define MASK_FCVT_W_S 0xfff0007f</span><br><span> #define MATCH_FCVT_WU_S 0xc0100053</span><br><span>@@ -508,8 +547,8 @@</span><br><span> #define MASK_FCVT_L_S 0xfff0007f</span><br><span> #define MATCH_FCVT_LU_S 0xc0300053</span><br><span> #define MASK_FCVT_LU_S 0xfff0007f</span><br><span style="color: hsl(0, 100%, 40%);">-#define MATCH_FMV_X_S 0xe0000053</span><br><span style="color: hsl(0, 100%, 40%);">-#define MASK_FMV_X_S 0xfff0707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMV_X_W 0xe0000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMV_X_W 0xfff0707f</span><br><span> #define MATCH_FCLASS_S 0xe0001053</span><br><span> #define MASK_FCLASS_S 0xfff0707f</span><br><span> #define MATCH_FCVT_W_D 0xc2000053</span><br><span>@@ -524,6 +563,18 @@</span><br><span> #define MASK_FMV_X_D 0xfff0707f</span><br><span> #define MATCH_FCLASS_D 0xe2001053</span><br><span> #define MASK_FCLASS_D 0xfff0707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_W_Q 0xc6000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_W_Q 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_WU_Q 0xc6100053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_WU_Q 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_L_Q 0xc6200053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_L_Q 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_LU_Q 0xc6300053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_LU_Q 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMV_X_Q 0xe6000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMV_X_Q 0xfff0707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCLASS_Q 0xe6001053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCLASS_Q 0xfff0707f</span><br><span> #define MATCH_FCVT_S_W 0xd0000053</span><br><span> #define MASK_FCVT_S_W 0xfff0007f</span><br><span> #define MATCH_FCVT_S_WU 0xd0100053</span><br><span>@@ -532,8 +583,8 @@</span><br><span> #define MASK_FCVT_S_L 0xfff0007f</span><br><span> #define MATCH_FCVT_S_LU 0xd0300053</span><br><span> #define MASK_FCVT_S_LU 0xfff0007f</span><br><span style="color: hsl(0, 100%, 40%);">-#define MATCH_FMV_S_X 0xf0000053</span><br><span style="color: hsl(0, 100%, 40%);">-#define MASK_FMV_S_X 0xfff0707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMV_W_X 0xf0000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMV_W_X 0xfff0707f</span><br><span> #define MATCH_FCVT_D_W 0xd2000053</span><br><span> #define MASK_FCVT_D_W 0xfff0007f</span><br><span> #define MATCH_FCVT_D_WU 0xd2100053</span><br><span>@@ -544,14 +595,28 @@</span><br><span> #define MASK_FCVT_D_LU 0xfff0007f</span><br><span> #define MATCH_FMV_D_X 0xf2000053</span><br><span> #define MASK_FMV_D_X 0xfff0707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_Q_W 0xd6000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_Q_W 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_Q_WU 0xd6100053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_Q_WU 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_Q_L 0xd6200053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_Q_L 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FCVT_Q_LU 0xd6300053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FCVT_Q_LU 0xfff0007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMV_Q_X 0xf6000053</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMV_Q_X 0xfff0707f</span><br><span> #define MATCH_FLW 0x2007</span><br><span> #define MASK_FLW 0x707f</span><br><span> #define MATCH_FLD 0x3007</span><br><span> #define MASK_FLD 0x707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FLQ 0x4007</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FLQ 0x707f</span><br><span> #define MATCH_FSW 0x2027</span><br><span> #define MASK_FSW 0x707f</span><br><span> #define MATCH_FSD 0x3027</span><br><span> #define MASK_FSD 0x707f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FSQ 0x4027</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FSQ 0x707f</span><br><span> #define MATCH_FMADD_S 0x43</span><br><span> #define MASK_FMADD_S 0x600007f</span><br><span> #define MATCH_FMSUB_S 0x47</span><br><span>@@ -568,6 +633,14 @@</span><br><span> #define MASK_FNMSUB_D 0x600007f</span><br><span> #define MATCH_FNMADD_D 0x200004f</span><br><span> #define MASK_FNMADD_D 0x600007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMADD_Q 0x6000043</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMADD_Q 0x600007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FMSUB_Q 0x6000047</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FMSUB_Q 0x600007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FNMSUB_Q 0x600004b</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FNMSUB_Q 0x600007f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MATCH_FNMADD_Q 0x600004f</span><br><span style="color: hsl(120, 100%, 40%);">+#define MASK_FNMADD_Q 0x600007f</span><br><span> #define MATCH_C_NOP 0x1</span><br><span> #define MASK_C_NOP 0xffff</span><br><span> #define MATCH_C_ADDI16SP 0x6101</span><br><span>@@ -738,23 +811,45 @@</span><br><span> #define CSR_SSTATUS 0x100</span><br><span> #define CSR_SIE 0x104</span><br><span> #define CSR_STVEC 0x105</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_SCOUNTEREN 0x106</span><br><span> #define CSR_SSCRATCH 0x140</span><br><span> #define CSR_SEPC 0x141</span><br><span> #define CSR_SCAUSE 0x142</span><br><span style="color: hsl(0, 100%, 40%);">-#define CSR_SBADADDR 0x143</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_STVAL 0x143</span><br><span> #define CSR_SIP 0x144</span><br><span style="color: hsl(0, 100%, 40%);">-#define CSR_SPTBR 0x180</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_SATP 0x180</span><br><span> #define CSR_MSTATUS 0x300</span><br><span> #define CSR_MISA 0x301</span><br><span> #define CSR_MEDELEG 0x302</span><br><span> #define CSR_MIDELEG 0x303</span><br><span> #define CSR_MIE 0x304</span><br><span> #define CSR_MTVEC 0x305</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_MCOUNTEREN 0x306</span><br><span> #define CSR_MSCRATCH 0x340</span><br><span> #define CSR_MEPC 0x341</span><br><span> #define CSR_MCAUSE 0x342</span><br><span style="color: hsl(0, 100%, 40%);">-#define CSR_MBADADDR 0x343</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_MTVAL 0x343</span><br><span> #define CSR_MIP 0x344</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPCFG0 0x3a0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPCFG1 0x3a1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPCFG2 0x3a2</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPCFG3 0x3a3</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR0 0x3b0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR1 0x3b1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR2 0x3b2</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR3 0x3b3</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR4 0x3b4</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR5 0x3b5</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR6 0x3b6</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR7 0x3b7</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR8 0x3b8</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR9 0x3b9</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR10 0x3ba</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR11 0x3bb</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR12 0x3bc</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR13 0x3bd</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR14 0x3be</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSR_PMPADDR15 0x3bf</span><br><span> #define CSR_TSELECT 0x7a0</span><br><span> #define CSR_TDATA1 0x7a1</span><br><span> #define CSR_TDATA2 0x7a2</span><br><span>@@ -793,8 +888,6 @@</span><br><span> #define CSR_MHPMCOUNTER29 0xb1d</span><br><span> #define CSR_MHPMCOUNTER30 0xb1e</span><br><span> #define CSR_MHPMCOUNTER31 0xb1f</span><br><span style="color: hsl(0, 100%, 40%);">-#define CSR_MUCOUNTEREN 0x320</span><br><span style="color: hsl(0, 100%, 40%);">-#define CSR_MSCOUNTEREN 0x321</span><br><span> #define CSR_MHPMEVENT3 0x323</span><br><span> #define CSR_MHPMEVENT4 0x324</span><br><span> #define CSR_MHPMEVENT5 0x325</span><br><span>@@ -892,17 +985,20 @@</span><br><span> #define CSR_MHPMCOUNTER30H 0xb9e</span><br><span> #define CSR_MHPMCOUNTER31H 0xb9f</span><br><span> #define CAUSE_MISALIGNED_FETCH 0x0</span><br><span style="color: hsl(0, 100%, 40%);">-#define CAUSE_FAULT_FETCH 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAUSE_FETCH_ACCESS 0x1</span><br><span> #define CAUSE_ILLEGAL_INSTRUCTION 0x2</span><br><span> #define CAUSE_BREAKPOINT 0x3</span><br><span> #define CAUSE_MISALIGNED_LOAD 0x4</span><br><span style="color: hsl(0, 100%, 40%);">-#define CAUSE_FAULT_LOAD 0x5</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAUSE_LOAD_ACCESS 0x5</span><br><span> #define CAUSE_MISALIGNED_STORE 0x6</span><br><span style="color: hsl(0, 100%, 40%);">-#define CAUSE_FAULT_STORE 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAUSE_STORE_ACCESS 0x7</span><br><span> #define CAUSE_USER_ECALL 0x8</span><br><span> #define CAUSE_SUPERVISOR_ECALL 0x9</span><br><span> #define CAUSE_HYPERVISOR_ECALL 0xa</span><br><span> #define CAUSE_MACHINE_ECALL 0xb</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAUSE_FETCH_PAGE_FAULT 0xc</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAUSE_LOAD_PAGE_FAULT 0xd</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAUSE_STORE_PAGE_FAULT 0xf</span><br><span> #endif</span><br><span> #ifdef DECLARE_INSN</span><br><span> DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)</span><br><span>@@ -995,10 +1091,9 @@</span><br><span> DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)</span><br><span> DECLARE_INSN(uret, MATCH_URET, MASK_URET)</span><br><span> DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)</span><br><span> DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)</span><br><span> DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)</span><br><span> DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)</span><br><span> DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)</span><br><span> DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)</span><br><span>@@ -1028,17 +1123,34 @@</span><br><span> DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)</span><br><span> DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)</span><br><span> DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)</span><br><span> DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)</span><br><span> DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)</span><br><span> DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)</span><br><span> DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)</span><br><span> DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)</span><br><span> DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)</span><br><span> DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)</span><br><span> DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)</span><br><span> DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)</span><br><span> DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)</span><br><span> DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)</span><br><span> DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)</span><br><span> DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)</span><br><span>@@ -1046,20 +1158,33 @@</span><br><span> DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)</span><br><span> DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)</span><br><span> DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)</span><br><span> DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)</span><br><span> DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)</span><br><span> DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)</span><br><span> DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)</span><br><span> DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)</span><br><span> DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)</span><br><span> DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)</span><br><span> DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)</span><br><span> DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)</span><br><span> DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)</span><br><span> DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)</span><br><span> DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)</span><br><span> DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)</span><br><span> DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)</span><br><span> DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)</span><br><span> DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)</span><br><span>@@ -1068,6 +1193,10 @@</span><br><span> DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)</span><br><span> DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)</span><br><span> DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)</span><br><span> DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)</span><br><span> DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)</span><br><span> DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)</span><br><span>@@ -1174,23 +1303,45 @@</span><br><span> DECLARE_CSR(sstatus, CSR_SSTATUS)</span><br><span> DECLARE_CSR(sie, CSR_SIE)</span><br><span> DECLARE_CSR(stvec, CSR_STVEC)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)</span><br><span> DECLARE_CSR(sscratch, CSR_SSCRATCH)</span><br><span> DECLARE_CSR(sepc, CSR_SEPC)</span><br><span> DECLARE_CSR(scause, CSR_SCAUSE)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CSR(sbadaddr, CSR_SBADADDR)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(stval, CSR_STVAL)</span><br><span> DECLARE_CSR(sip, CSR_SIP)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CSR(sptbr, CSR_SPTBR)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(satp, CSR_SATP)</span><br><span> DECLARE_CSR(mstatus, CSR_MSTATUS)</span><br><span> DECLARE_CSR(misa, CSR_MISA)</span><br><span> DECLARE_CSR(medeleg, CSR_MEDELEG)</span><br><span> DECLARE_CSR(mideleg, CSR_MIDELEG)</span><br><span> DECLARE_CSR(mie, CSR_MIE)</span><br><span> DECLARE_CSR(mtvec, CSR_MTVEC)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)</span><br><span> DECLARE_CSR(mscratch, CSR_MSCRATCH)</span><br><span> DECLARE_CSR(mepc, CSR_MEPC)</span><br><span> DECLARE_CSR(mcause, CSR_MCAUSE)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CSR(mbadaddr, CSR_MBADADDR)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(mtval, CSR_MTVAL)</span><br><span> DECLARE_CSR(mip, CSR_MIP)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)</span><br><span> DECLARE_CSR(tselect, CSR_TSELECT)</span><br><span> DECLARE_CSR(tdata1, CSR_TDATA1)</span><br><span> DECLARE_CSR(tdata2, CSR_TDATA2)</span><br><span>@@ -1229,8 +1380,6 @@</span><br><span> DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)</span><br><span> DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)</span><br><span> DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)</span><br><span> DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)</span><br><span> DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)</span><br><span> DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)</span><br><span>@@ -1327,20 +1476,21 @@</span><br><span> DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)</span><br><span> DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)</span><br><span> DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #ifdef DECLARE_CAUSE</span><br><span> DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)</span><br><span> DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)</span><br><span> DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)</span><br><span> DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)</span><br><span> DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)</span><br><span style="color: hsl(0, 100%, 40%);">-DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)</span><br><span> DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)</span><br><span> DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)</span><br><span> DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)</span><br><span> DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)</span><br><span style="color: hsl(120, 100%, 40%);">+DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* RISCV_CSR_ENCODING_H */</span><br><span>diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c</span><br><span>index 8fd0375..7b35c2e 100644</span><br><span>--- a/src/arch/riscv/trap_handler.c</span><br><span>+++ b/src/arch/riscv/trap_handler.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/encoding.h></span><br><span> #include <arch/exception.h></span><br><span> #include <console/console.h></span><br><span> #include <string.h></span><br><span>@@ -33,8 +34,12 @@</span><br><span> "Store access fault",</span><br><span> "Environment call from U-mode",</span><br><span> "Environment call from S-mode",</span><br><span style="color: hsl(0, 100%, 40%);">- "Environment call from H-mode",</span><br><span style="color: hsl(0, 100%, 40%);">- "Environment call from M-mode"</span><br><span style="color: hsl(120, 100%, 40%);">+ "Reserved (10)",</span><br><span style="color: hsl(120, 100%, 40%);">+ "Environment call from M-mode",</span><br><span style="color: hsl(120, 100%, 40%);">+ "Instruction page fault",</span><br><span style="color: hsl(120, 100%, 40%);">+ "Load page fault",</span><br><span style="color: hsl(120, 100%, 40%);">+ "Reserved (14)",</span><br><span style="color: hsl(120, 100%, 40%);">+ "Store page fault",</span><br><span> };</span><br><span> </span><br><span> static const char *mstatus_to_previous_mode(uintptr_t ms)</span><br><span>@@ -119,7 +124,7 @@</span><br><span> // at present, as we only search for</span><br><span> // "core{0{0{timecmp" above.</span><br><span> ssie = read_csr(sie);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!(ssie & SIE_STIE))</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(ssie & SIP_STIP))</span><br><span> break;</span><br><span> </span><br><span> if (!timecmp)</span><br><span>@@ -149,11 +154,11 @@</span><br><span> </span><br><span> switch(tf->cause) {</span><br><span> case CAUSE_MISALIGNED_FETCH:</span><br><span style="color: hsl(0, 100%, 40%);">- case CAUSE_FAULT_FETCH:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CAUSE_FETCH_ACCESS:</span><br><span> case CAUSE_ILLEGAL_INSTRUCTION:</span><br><span> case CAUSE_BREAKPOINT:</span><br><span style="color: hsl(0, 100%, 40%);">- case CAUSE_FAULT_LOAD:</span><br><span style="color: hsl(0, 100%, 40%);">- case CAUSE_FAULT_STORE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CAUSE_LOAD_ACCESS:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CAUSE_STORE_ACCESS:</span><br><span> case CAUSE_USER_ECALL:</span><br><span> case CAUSE_SUPERVISOR_ECALL:</span><br><span> case CAUSE_HYPERVISOR_ECALL:</span><br><span>diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c</span><br><span>index 702d6b7..3cc2cc9 100644</span><br><span>--- a/src/arch/riscv/virtual_memory.c</span><br><span>+++ b/src/arch/riscv/virtual_memory.c</span><br><span>@@ -26,11 +26,11 @@</span><br><span> * the spec so for now we enumerate and set them all. */</span><br><span> static int delegate = 0</span><br><span> | (1 << CAUSE_MISALIGNED_FETCH)</span><br><span style="color: hsl(0, 100%, 40%);">- | (1 << CAUSE_FAULT_FETCH)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (1 << CAUSE_FETCH_ACCESS)</span><br><span> | (1 << CAUSE_ILLEGAL_INSTRUCTION)</span><br><span> | (1 << CAUSE_BREAKPOINT)</span><br><span style="color: hsl(0, 100%, 40%);">- | (1 << CAUSE_FAULT_LOAD)</span><br><span style="color: hsl(0, 100%, 40%);">- | (1 << CAUSE_FAULT_STORE)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (1 << CAUSE_LOAD_ACCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (1 << CAUSE_STORE_ACCESS)</span><br><span> | (1 << CAUSE_USER_ECALL)</span><br><span> ;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23773">change 23773</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23773"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8 </div>
<div style="display:none"> Gerrit-Change-Number: 23773 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>