<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23754">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Only enable CAR if DRAM PLL isn't running<br><br>Change-Id: I76f1a44c215f933af74f4d659de59013f2677dad<br>---<br>M src/soc/cavium/cn81xx/bootblock.c<br>M src/soc/cavium/cn81xx/bootblock_custom.S<br>2 files changed, 16 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/23754/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c</span><br><span>index ea83369..9517fb7 100644</span><br><span>--- a/src/soc/cavium/cn81xx/bootblock.c</span><br><span>+++ b/src/soc/cavium/cn81xx/bootblock.c</span><br><span>@@ -26,19 +26,6 @@</span><br><span> #include <program_loading.h></span><br><span> #include <timestamp.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int is_dram_enabled(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-    BDK_CSR_INIT(lmcx_ddr_pll_ctl, node, BDK_LMCX_DDR_PLL_CTL(0));</span><br><span style="color: hsl(0, 100%, 40%);">-    if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))</span><br><span style="color: hsl(0, 100%, 40%);">-        return lmcx_ddr_pll_ctl.cn83xx.reset_n;</span><br><span style="color: hsl(0, 100%, 40%);">-    else</span><br><span style="color: hsl(0, 100%, 40%);">-        return !lmcx_ddr_pll_ctl.cn9.pll_reset;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-    /* FIXME: stub - see __bdk_is_dram_enabled for reference code */</span><br><span style="color: hsl(0, 100%, 40%);">-    return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void init_sysreg(void)</span><br><span> {</span><br><span> #if 0</span><br><span>@@ -105,9 +92,6 @@</span><br><span> </span><br><span> void bootblock_soc_early_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    /* Only lock L2 if DDR3 isn't initialized */</span><br><span style="color: hsl(0, 100%, 40%);">-        if (is_dram_enabled())</span><br><span style="color: hsl(0, 100%, 40%);">-          return;</span><br><span> </span><br><span>  /* FIXME: will cache_sync_instructions() do? */</span><br><span>      //cache_sync_instructions();</span><br><span>diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>index d3eae1d..00a6aff 100644</span><br><span>--- a/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>+++ b/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>@@ -50,6 +50,22 @@</span><br><span>     #error Unknown endianness</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+    #define BDK_LMCX 0x87e088000000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+    #define DDR_PLL_CTL0 0x258</span><br><span style="color: hsl(120, 100%, 40%);">+    mov     x0, (BDK_LMCX >> 32)</span><br><span style="color: hsl(120, 100%, 40%);">+    lsl     x0, x0, 32</span><br><span style="color: hsl(120, 100%, 40%);">+    mov     x1, (BDK_LMCX & 0xffffffff)</span><br><span style="color: hsl(120, 100%, 40%);">+    orr     x0, x0, x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    /* Test if DRAM PLL is running */</span><br><span style="color: hsl(120, 100%, 40%);">+    ldr     x1, [x0, DDR_PLL_CTL0]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    tst     x1, 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+    #undef BDK_LMCX</span><br><span style="color: hsl(120, 100%, 40%);">+    #undef DDR_PLL_CTL0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    b.ne     cache_setup_done</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>     bl      _setup_car</span><br><span> </span><br><span> cache_setup_done:</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23754">change 23754</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23754"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I76f1a44c215f933af74f4d659de59013f2677dad </div>
<div style="display:none"> Gerrit-Change-Number: 23754 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>