<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23753">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Add GPIO driver<br><br>Change-Id: I77b83eaebc94b1e311e6834658074c2c7c5faf55<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/soc/cavium/cn81xx/Makefile.inc<br>M src/soc/cavium/common/Makefile.inc<br>M src/soc/cavium/common/gpio.c<br>M src/soc/cavium/common/include/soc/gpio.h<br>4 files changed, 169 insertions(+), 174 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/23753/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>index 8fe8f44..6c129e8 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>+++ b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>@@ -70,7 +70,6 @@</span><br><span> romstage-y += ../common/lame_string.c</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #verstage-y += ../common/cbmem.c</span><br><span> #verstage-y += ../common/gpio.c</span><br><span> #verstage-y += gpio.c</span><br><span>diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc</span><br><span>index 48cc7bd..f51e13e 100644</span><br><span>--- a/src/soc/cavium/common/Makefile.inc</span><br><span>+++ b/src/soc/cavium/common/Makefile.inc</span><br><span>@@ -18,16 +18,19 @@</span><br><span> bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c</span><br><span> bootblock-y += twsi.c</span><br><span> bootblock-y += clock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span> </span><br><span> </span><br><span> </span><br><span> romstage-y += twsi.c</span><br><span> romstage-y += clock.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span> </span><br><span> </span><br><span> </span><br><span> ramstage-y += twsi.c</span><br><span> ramstage-y += clock.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span> </span><br><span> CPPFLAGS_common += -Isrc/soc/cavium/common/include</span><br><span> </span><br><span>diff --git a/src/soc/cavium/common/gpio.c b/src/soc/cavium/common/gpio.c</span><br><span>index add2100..b7620e5 100644</span><br><span>--- a/src/soc/cavium/common/gpio.c</span><br><span>+++ b/src/soc/cavium/common/gpio.c</span><br><span>@@ -1,138 +1,183 @@</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018-present Facebook, Inc.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPDX-License-Identifier: GPL-2.0+</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* FIXME: scaffolding based on rk3399 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <assert.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span> #include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-//#include <soc/grf.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/soc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <endian.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir)</span><br><span style="color: hsl(120, 100%, 40%);">+union gpio_const {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 u;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 gpios:8; /** Number of GPIOs implemented */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 pp:8; /** Number of PP vectors */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64:48; /* Reserved */</span><br><span style="color: hsl(120, 100%, 40%);">+ } s;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+union bit_cfg {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 u;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tx_oe : 1; /* Output Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 xor : 1; /* Invert */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 int_en : 1; /* Interrupt Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 int_type : 1; /* Type of Interrupt */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 filt_cnt : 4; /* Glitch filter counter */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 filt_sel : 4; /* Glitch filter select */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tx_od : 1; /* Set Output to Open Drain */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 : 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 pin_sel : 10; /* Select type of pin */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 : 38;</span><br><span style="color: hsl(120, 100%, 40%);">+ } s;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct cavium_gpio {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rx_dat;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tx_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tx_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 multicast;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ocla_exten_trg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 strap;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 reserved[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ union gpio_const gpio_const; /* Offset 90 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 reserved2[109];</span><br><span style="color: hsl(120, 100%, 40%);">+ union bit_cfg bit_cfg[48]; /* Offset 400 */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Base address of GPIO BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+static void *gpio_get_baseaddr(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr,</span><br><span style="color: hsl(0, 100%, 40%);">- 1 << gpio.num, dir << gpio.num);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)0x803000000000ULL;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Number of GPIO pins. Usually 48. */</span><br><span style="color: hsl(120, 100%, 40%);">+gpio_t gpio_pin_count(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pull_val = gpio_get_pull_val(gpio, pull);</span><br><span style="color: hsl(0, 100%, 40%);">- if (is_pmu_gpio(gpio) && IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288))</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2),</span><br><span style="color: hsl(0, 100%, 40%);">- pull_val << (gpio.idx * 2));</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2),</span><br><span style="color: hsl(0, 100%, 40%);">- pull_val << (gpio.idx * 2)));</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr();</span><br><span style="color: hsl(120, 100%, 40%);">+ union gpio_const gpio_const;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_const.u = read64(®s->gpio_const.u);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio_const.s.gpios > 64)</span><br><span style="color: hsl(120, 100%, 40%);">+ return 64; // FIXME: Add support for more than 64 GPIOs</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_const.s.gpios;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Set GPIO to software control and direction INPUT */</span><br><span> void gpio_input(gpio_t gpio)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_pull(gpio, GPIO_PULLNONE);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_dir(gpio, GPIO_INPUT);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr();</span><br><span style="color: hsl(120, 100%, 40%);">+ union bit_cfg bit_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio >= gpio_pin_count())</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "GPIO(%u): direction input\n", gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.u = read64(®s->bit_cfg[gpio]);</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.s.pin_sel = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.s.tx_oe = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ write64(®s->bit_cfg[gpio], bit_cfg.u);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set GPIO of direction OUTPUT to level */</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_set(gpio_t gpio, int value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio >= gpio_pin_count())</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "GPIO(%u): level: %u\n", gpio, !!value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (value)</span><br><span style="color: hsl(120, 100%, 40%);">+ write64(®s->tx_set, 1 << gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ write64(®s->tx_clr, 1 << gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set GPIO direction to OUTPUT with level */</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_output(gpio_t gpio, int value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr();</span><br><span style="color: hsl(120, 100%, 40%);">+ union bit_cfg bit_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio >= gpio_pin_count())</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set(gpio, value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "GPIO(%u): direction output with level: %u\n", gpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ !!value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.u = read64(®s->bit_cfg[gpio]);</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.s.pin_sel = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.s.tx_oe = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ write64(®s->bit_cfg[gpio], bit_cfg.u);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set GPIO invert flag, that affects INPUT and OUTPUT */</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_invert(gpio_t gpio, int value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr();</span><br><span style="color: hsl(120, 100%, 40%);">+ union bit_cfg bit_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio >= gpio_pin_count())</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.u = read64(®s->bit_cfg[gpio]);</span><br><span style="color: hsl(120, 100%, 40%);">+ bit_cfg.s.xor = !!value;</span><br><span style="color: hsl(120, 100%, 40%);">+ write64(®s->bit_cfg[gpio], bit_cfg.u);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "GPIO(%u): invert: %s\n", gpio, value ? "ON" : "OFF");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Read GPIO level with direction set to INPUT */</span><br><span style="color: hsl(120, 100%, 40%);">+int gpio_get(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio >= gpio_pin_count())</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const u64 reg = read64(®s->rx_dat);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "GPIO(%u): input: %u\n", gpio, !!(reg & (1 << gpio)));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(reg & (1 << gpio));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Read GPIO STRAP level sampled at cold boot */</span><br><span style="color: hsl(120, 100%, 40%);">+int gpio_strap_value(gpio_t gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio >= gpio_pin_count())</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const u64 reg = read64(®s->strap);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "GPIO(%u): strap: %u\n", gpio, !!(reg & (1 << gpio)));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(reg & (1 << gpio));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* FIXME: Parse devicetree ? */</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t pin_count = gpio_pin_count();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GPIO: base address: %p, pin count: %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_get_baseaddr(), pin_count);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!pin_count)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span> }</span><br><span> </span><br><span> void gpio_input_pulldown(gpio_t gpio)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_pull(gpio, GPIO_PULLDOWN);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_dir(gpio, GPIO_INPUT);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span> void gpio_input_pullup(gpio_t gpio)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_pull(gpio, GPIO_PULLUP);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_dir(gpio, GPIO_INPUT);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t int_polarity, inttype_level;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mask = BIT(gpio.num);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* gpio pull only PULLNONE, PULLUP, PULLDOWN status */</span><br><span style="color: hsl(0, 100%, 40%);">- assert(pull <= GPIO_PULLDOWN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_dir(gpio, GPIO_INPUT);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_pull(gpio, pull);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int_polarity = inttype_level = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- switch (type) {</span><br><span style="color: hsl(0, 100%, 40%);">- case IRQ_TYPE_EDGE_RISING:</span><br><span style="color: hsl(0, 100%, 40%);">- int_polarity = mask;</span><br><span style="color: hsl(0, 100%, 40%);">- inttype_level = mask;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case IRQ_TYPE_EDGE_FALLING:</span><br><span style="color: hsl(0, 100%, 40%);">- inttype_level = mask;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case IRQ_TYPE_LEVEL_HIGH:</span><br><span style="color: hsl(0, 100%, 40%);">- int_polarity = mask;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case IRQ_TYPE_LEVEL_LOW:</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&gpio_port[gpio.port]->int_polarity,</span><br><span style="color: hsl(0, 100%, 40%);">- mask, int_polarity);</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&gpio_port[gpio.port]->inttype_level,</span><br><span style="color: hsl(0, 100%, 40%);">- mask, inttype_level);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&gpio_port[gpio.port]->inten, mask);</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&gpio_port[gpio.port]->intmask, mask);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int gpio_irq_status(gpio_t gpio)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mask = BIT(gpio.num);</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t int_status = read32(&gpio_port[gpio.port]->int_status);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!(int_status & mask))</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&gpio_port[gpio.port]->porta_eoi, mask);</span><br><span style="color: hsl(0, 100%, 40%);">- return 1;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int gpio_get(gpio_t gpio)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void gpio_output(gpio_t gpio, int value)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,</span><br><span style="color: hsl(0, 100%, 40%);">- !!value << gpio.num);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_dir(gpio, GPIO_OUTPUT);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_pull(gpio, GPIO_PULLNONE);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span>diff --git a/src/soc/cavium/common/include/soc/gpio.h b/src/soc/cavium/common/include/soc/gpio.h</span><br><span>index 666f7bb..6986482 100644</span><br><span>--- a/src/soc/cavium/common/include/soc/gpio.h</span><br><span>+++ b/src/soc/cavium/common/include/soc/gpio.h</span><br><span>@@ -19,68 +19,16 @@</span><br><span> </span><br><span> #include <types.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef union {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 raw;</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- struct {</span><br><span style="color: hsl(0, 100%, 40%);">- union {</span><br><span style="color: hsl(0, 100%, 40%);">- struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 num : 5;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved1 : 27;</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 idx : 3;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 bank : 2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 port : 4;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved2 : 23;</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-} gpio_t;</span><br><span style="color: hsl(120, 100%, 40%);">+typedef u32 gpio_t;</span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-enum {</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_A = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_B,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_C,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_D,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(120, 100%, 40%);">+/* The following functions must be implemented by SoC/board code. */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-extern struct rockchip_gpio_regs *gpio_port[];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Check if the gpio port is a pmu gpio */</span><br><span style="color: hsl(0, 100%, 40%);">-int is_pmu_gpio(gpio_t gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+gpio_t gpio_pin_count(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_invert(gpio_t gpio, int value);</span><br><span style="color: hsl(120, 100%, 40%);">+int gpio_strap_value(gpio_t gpio);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Return the io addr of gpio register */</span><br><span style="color: hsl(0, 100%, 40%);">-void *gpio_grf_reg(gpio_t gpio);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enum gpio_pull {</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_PULLNONE = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_PULLUP = 1,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_PULLDOWN = 2,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enum gpio_dir {</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_INPUT = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_OUTPUT = 1,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enum gpio_irq_type {</span><br><span style="color: hsl(0, 100%, 40%);">- IRQ_TYPE_EDGE_RISING = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- IRQ_TYPE_EDGE_FALLING,</span><br><span style="color: hsl(0, 100%, 40%);">- IRQ_TYPE_LEVEL_HIGH,</span><br><span style="color: hsl(0, 100%, 40%);">- IRQ_TYPE_LEVEL_LOW,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Setup and enable irq */</span><br><span style="color: hsl(0, 100%, 40%);">-void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Check and clear irq status */</span><br><span style="color: hsl(0, 100%, 40%);">-int gpio_irq_status(gpio_t gpio);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* The gpio pull bias setting may be different between SoCs */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+void gpio_init(void);</span><br><span> </span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23753">change 23753</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I77b83eaebc94b1e311e6834658074c2c7c5faf55 </div>
<div style="display:none"> Gerrit-Change-Number: 23753 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>