<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23752">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Implement common clock system<br><br>Get rid of cn81xx custom clock code.<br>Fix UART divisor.<br><br>Change-Id: Ifc4fdbaeec78e2fbc956b4821730f2c16f779b91<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/soc/cavium/cn81xx/Makefile.inc<br>D src/soc/cavium/cn81xx/clock.c<br>D src/soc/cavium/cn81xx/include/soc/clock.h<br>M src/soc/cavium/cn81xx/include/soc/soc.h<br>M src/soc/cavium/cn81xx/timer.c<br>M src/soc/cavium/cn81xx/uart.c<br>M src/soc/cavium/common/Makefile.inc<br>A src/soc/cavium/common/clock.c<br>M src/soc/cavium/common/include/soc/bdk/libbdk-hal/bdk-clock.h<br>A src/soc/cavium/common/include/soc/clock.h<br>M src/soc/cavium/common/twsi.c<br>M src/soc/cavium/common/wdt.c<br>12 files changed, 128 insertions(+), 197 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/23752/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>index fbba930..8fe8f44 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>+++ b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>@@ -26,7 +26,6 @@</span><br><span> #bootblock-y += ../common/gpio.c</span><br><span> #bootblock-y += ../common/pwm.c</span><br><span> bootblock-y += bootblock.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += clock.c</span><br><span> #bootblock-y += gpio.c</span><br><span> bootblock-y += twsi.c</span><br><span> bootblock-y += l2c.c</span><br><span>@@ -79,7 +78,6 @@</span><br><span> #verstage-y += ../common/i2c.c</span><br><span> #verstage-y += spi.c</span><br><span> #verstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-#verstage-y += clock.c</span><br><span> #verstage-y += timer.c</span><br><span> verstage-y += ../common/wdt.c</span><br><span> </span><br><span>@@ -88,7 +86,6 @@</span><br><span> romstage-y += ../common/cbmem.c</span><br><span> romstage-y += spi.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += clock.c</span><br><span> romstage-y += mmu_operations.c</span><br><span> #romstage-y += ../common/pwm.c</span><br><span> romstage-y += timer.c</span><br><span>@@ -103,7 +100,6 @@</span><br><span> ramstage-y += spi.c</span><br><span> ramstage-y += twsi.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-##ramstage-y += clock.c</span><br><span> #ramstage-y += ../common/gpio.c</span><br><span> #ramstage-y += gpio.c</span><br><span> #ramstage-y += ../common/i2c.c</span><br><span>diff --git a/src/soc/cavium/cn81xx/clock.c b/src/soc/cavium/cn81xx/clock.c</span><br><span>deleted file mode 100644</span><br><span>index 0af466c..0000000</span><br><span>--- a/src/soc/cavium/cn81xx/clock.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,37 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * SPDX-License-Identifier: BSD-3-Clause</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <libbdk-hal/bdk-clock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/addressmap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/clock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/soc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/timer.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uint64_t clock_get_rate(bdk_clock_t source)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct cn81xx_rst *rst = (struct cn81xx_rst *)RST_PF_BAR0;</span><br><span style="color: hsl(0, 100%, 40%);">- const uint64_t REF_CLOCK = BDK_REF_CLOCK;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u64 mul = read64(&rst->boot);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- switch (source) {</span><br><span style="color: hsl(0, 100%, 40%);">- case BDK_CLOCK_TIME:</span><br><span style="color: hsl(0, 100%, 40%);">- return BDK_GTI_RATE; /* Programed as part of setup */</span><br><span style="color: hsl(0, 100%, 40%);">- case BDK_CLOCK_MAIN_REF:</span><br><span style="color: hsl(0, 100%, 40%);">- return REF_CLOCK;</span><br><span style="color: hsl(0, 100%, 40%);">- case BDK_CLOCK_RCLK:</span><br><span style="color: hsl(0, 100%, 40%);">- mul = (mul >> RST_BOOT_C_MUL_SHIFT) & RST_BOOT_C_MUL_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">- return REF_CLOCK * mul;</span><br><span style="color: hsl(0, 100%, 40%);">- case BDK_CLOCK_SCLK:</span><br><span style="color: hsl(0, 100%, 40%);">- mul = (mul >> RST_BOOT_PNR_MUL_SHIFT) & RST_BOOT_PNR_MUL_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">- return REF_CLOCK * mul;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/clock.h b/src/soc/cavium/cn81xx/include/soc/clock.h</span><br><span>deleted file mode 100644</span><br><span>index ad535e0..0000000</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/clock.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,47 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights</span><br><span style="color: hsl(0, 100%, 40%);">- * reserved.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * SPDX-License-Identifier: BSD-3-Clause</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __SOC_CAVIUM_CN81XX_CLOCK_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __SOC_CAVIUM_CN81XX_CLOCK_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <commonlib/helpers.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <libbdk-arch/bdk-numa.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <libbdk-hal/bdk-clock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/addressmap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <types.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-enum cn81xx_clock_source {</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_CLOCK_TIME, /* Clock for telling time with fast access. Uses GTI in core */</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_CLOCK_MAIN_REF, /* Main reference clock */</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_CLOCK_RCLK, /* Clock used by cores, coherent bus and L2 cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_CLOCK_SCLK, /* Clock used by IO blocks. */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define BDK_REF_CLOCK 50000000ULL</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-uint64_t clock_get_rate(enum cn81xx_clock_source);</span><br><span style="color: hsl(0, 100%, 40%);">-static inline uint64_t bdk_clock_get_rate(bdk_node_t node, enum cn81xx_clock_source clock)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return clock_get_rate((enum cn81xx_clock_source)clock);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/* FIXME(dhendrix): ...and later moved into bdk-clock.h... */</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-uint64_t clock_get_rate(bdk_clock_t clock);</span><br><span style="color: hsl(0, 100%, 40%);">-static inline uint64_t clock_get_rate_slow(bdk_clock_t clock)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- clock_get_rate(clock);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __SOC_CAVIUM_CN81XX_CLOCK_H__ */</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/soc.h b/src/soc/cavium/cn81xx/include/soc/soc.h</span><br><span>index d1f200b..a751e64 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/soc.h</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/soc.h</span><br><span>@@ -19,72 +19,6 @@</span><br><span> #include <inttypes.h></span><br><span> #include <types.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* RST registers */</span><br><span style="color: hsl(0, 100%, 40%);">-struct cn81xx_rst {</span><br><span style="color: hsl(0, 100%, 40%);">- u64 boot;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 delay;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 cfg;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ocx;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd1[0x8];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 intr;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 intr_w1s;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ckill;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ctl0;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ctl1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ctl2;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd2[0x28];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 soft_rst;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 out_ctl;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 thermal_alert;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd3[0x8];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 int_ena_w1s;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 int_ena_w1c;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd4[0x10];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 soft_prst0;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 soft_prst1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 soft_prst2;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd5[0x28];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 pp_power;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 power_dbg;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 pp_power_stat;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd6[0x20];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 pp_available;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 pp_reset;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 pp_pending;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd7[0x8];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ref_cntr;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd8[0x50];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 debug;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd9[0x8];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 cold_data0;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 cold_data1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 cold_data2;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 cold_data3;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 cold_data4;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 cold_data5;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(cn81xx_rst, cold_data5, 0x17e8 - 0x1600);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_RBOOT_PIN (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_RBOOT (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_LBOOT_SHIFT 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_LBOOT_MASK 0x3ff</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_LBOOT_EXT23_SHIFT 12</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_LBOOT_EXT23_MASK 0x3f</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_LBOOT_JTG (1 << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_LBOOT_CKILL (1 << 25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_PNR_MUL_SHIFT 33</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_PNR_MUL_MASK 0x3f</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_C_MUL_SHIFT 40</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_C_MUL_MASK 0x7f</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_DIS_SCAN (1 << 55)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_DIS_HUK (1 << 56)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_JT_TSTMODE (1 << 58)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_CKILL_PPDIS (1 << 59)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_TRUSTED_MODE (1 << 60)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_JTCSRDIS (1 << 62)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT_CHIPKILL (1 << 63)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* MIO BOOT Registers */</span><br><span> struct cn81xx_mio_boot {</span><br><span> u8 rsvd0[0xb0];</span><br><span>diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c</span><br><span>index 3d59a40..a60d5cb 100644</span><br><span>--- a/src/soc/cavium/cn81xx/timer.c</span><br><span>+++ b/src/soc/cavium/cn81xx/timer.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> return;</span><br><span> </span><br><span> /* Configure GTI to tick at BDK_GTI_RATE */</span><br><span style="color: hsl(0, 100%, 40%);">- u64 sclk = clock_get_rate(BDK_CLOCK_SCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 sclk = thunderx_get_io_clock();</span><br><span> #if 0</span><br><span> /*</span><br><span> * FIXME(dhendrix): Had difficulty using reference code's way of</span><br><span>@@ -58,7 +58,7 @@</span><br><span> read32(>i->cc_cntcr); /* FIXME: is this needed? */</span><br><span> </span><br><span> /* Enable the core timer */</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_MSR(CNTFRQ_EL0, BDK_GTI_RATE); /* Needed for Asim (FIXME: not needed for HW?) */</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_MSR(CNTFRQ_EL0, 100000000ull); /* Needed for Asim (FIXME: not needed for HW?) */</span><br><span> #if 0</span><br><span> bdk_ap_cntps_ctl_el1_t cntps_ctl_el1;</span><br><span> cntps_ctl_el1.u = 0;</span><br><span>diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c</span><br><span>index b4759aa..aacca82 100644</span><br><span>--- a/src/soc/cavium/cn81xx/uart.c</span><br><span>+++ b/src/soc/cavium/cn81xx/uart.c</span><br><span>@@ -15,11 +15,22 @@</span><br><span> #include <stdint.h></span><br><span> #include <soc/clock.h></span><br><span> #include <soc/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART_SCLK_DIV 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static size_t uart_sclk_divisor(size_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u8 div[] = {1, 2, 4, 6, 8, 16, 24, 32};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(reg < ARRAY_SIZE(div));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return div[reg];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> unsigned int uart_platform_refclk(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: this probably isn't right */</span><br><span style="color: hsl(0, 100%, 40%);">- return BDK_REF_CLOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ return thunderx_get_io_clock() / uart_sclk_divisor(UART_SCLK_DIV);</span><br><span> }</span><br><span> </span><br><span> uintptr_t uart_platform_base(int idx)</span><br><span>@@ -45,7 +56,7 @@</span><br><span> c. Deassert the HCLK clock divider reset: UCTL_CTL[H_CLKDIV_RST] = 0. */</span><br><span> clrsetbits_le64(&uart->uctl_ctl,</span><br><span> UART_UCTL_CTL_H_CLKDIV_MASK << UART_UCTL_CTL_H_CLKDIV_SEL_SHIFT,</span><br><span style="color: hsl(0, 100%, 40%);">- 3 << UART_UCTL_CTL_H_CLKDIV_SEL_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ UART_SCLK_DIV << UART_UCTL_CTL_H_CLKDIV_SEL_SHIFT);</span><br><span> clrbits_le64(&uart->uctl_ctl, UART_UCTL_CTL_H_CLK_BYP_SEL);</span><br><span> setbits_le64(&uart->uctl_ctl, UART_UCTL_CTL_H_CLK_EN);</span><br><span> clrbits_le64(&uart->uctl_ctl, UART_UCTL_CTL_H_CLKDIV_RST);</span><br><span>@@ -78,7 +89,8 @@</span><br><span> This means BRDI = 1 and BRDF = 0.085.</span><br><span> Therefore, fractional part, BRDF = integer((0.085x64)+0.5) = 5</span><br><span> Generated baud rate divider = 1+5/64 = 1.078 */</span><br><span style="color: hsl(0, 100%, 40%);">- u64 divisor = clock_get_rate(BDK_CLOCK_SCLK) / (baudrate * 16 * 6 / 64);</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 divisor = thunderx_get_io_clock() /</span><br><span style="color: hsl(120, 100%, 40%);">+ (baudrate * 16 * uart_sclk_divisor(UART_SCLK_DIV) / 64);</span><br><span> write32(&uart->pl011.ibrd, divisor >> 6);</span><br><span> write32(&uart->pl011.fbrd, divisor & UART_FBRD_BAUD_DIVFRAC_MASK);</span><br><span> </span><br><span>diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc</span><br><span>index 6777dfc..48cc7bd 100644</span><br><span>--- a/src/soc/cavium/common/Makefile.inc</span><br><span>+++ b/src/soc/cavium/common/Makefile.inc</span><br><span>@@ -17,13 +17,17 @@</span><br><span> </span><br><span> bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c</span><br><span> bootblock-y += twsi.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += clock.c</span><br><span> </span><br><span> </span><br><span> </span><br><span> romstage-y += twsi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += clock.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> </span><br><span> ramstage-y += twsi.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += clock.c</span><br><span> </span><br><span> CPPFLAGS_common += -Isrc/soc/cavium/common/include</span><br><span> </span><br><span>diff --git a/src/soc/cavium/common/clock.c b/src/soc/cavium/common/clock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1a5664d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/cavium/common/clock.c</span><br><span>@@ -0,0 +1,71 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * (C) Copyright 2016, Cavium, Inc. <support@cavium.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Aaron Williams, <aaron.williams@cavium.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPDX-License-Identifier: GPL-2.0+</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RST_BOOT ((void *const)0x87e006001600ll)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_REF_CLK 50000000 /* 50 MHz */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+union cavm_rst_boot {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 u;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rboot_pin:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rboot:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 lboot:10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 lboot_ext23:6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 lboot_ext45:6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 reserved_24_29:6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 lboot_oci:3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 pnr_mul:6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 reserved_39_39:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 c_mul:7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 reserved_47_54:8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 dis_scan:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 dis_huk:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 vrm_err:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 jt_tstmode:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ckill_ppdis:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 trusted_mode:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ejtagdis:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 jtcsrdis:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 chipkill:1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } s;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Returns the reference clock speed in Hz</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+u64 thunderx_get_ref_clock(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return PLL_REF_CLK;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Returns the I/O clock speed in Hz</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+u64 thunderx_get_io_clock(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ union cavm_rst_boot rst_boot;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rst_boot.u = read64(RST_BOOT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return rst_boot.s.pnr_mul * PLL_REF_CLK;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Returns the core clock speed in Hz</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+u64 thunderx_get_core_clock(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ union cavm_rst_boot rst_boot;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rst_boot.u = read64(RST_BOOT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return rst_boot.s.c_mul * PLL_REF_CLK;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/cavium/common/include/soc/bdk/libbdk-hal/bdk-clock.h b/src/soc/cavium/common/include/soc/bdk/libbdk-hal/bdk-clock.h</span><br><span>index ce02223..9a22fde 100644</span><br><span>--- a/src/soc/cavium/common/include/soc/bdk/libbdk-hal/bdk-clock.h</span><br><span>+++ b/src/soc/cavium/common/include/soc/bdk/libbdk-hal/bdk-clock.h</span><br><span>@@ -42,6 +42,9 @@</span><br><span> /* FIXME(dhendrix): added */</span><br><span> #include <libbdk-arch/bdk-asm.h></span><br><span> #include <libbdk-arch/bdk-numa.h></span><br><span style="color: hsl(120, 100%, 40%);">+/* FIXME(prudolph): added */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span> </span><br><span> /**</span><br><span> * @file</span><br><span>@@ -66,10 +69,21 @@</span><br><span> BDK_CLOCK_SCLK, /**< Clock used by IO blocks. */</span><br><span> } bdk_clock_t;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uint64_t clock_get_rate(bdk_clock_t clock);</span><br><span> static inline uint64_t clock_get_rate_slow(bdk_clock_t clock)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- clock_get_rate(clock);</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint64_t REF_CLOCK = 50000000;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (clock) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case BDK_CLOCK_TIME:</span><br><span style="color: hsl(120, 100%, 40%);">+ return BDK_GTI_RATE; /* Programed as part of setup */</span><br><span style="color: hsl(120, 100%, 40%);">+ case BDK_CLOCK_MAIN_REF:</span><br><span style="color: hsl(120, 100%, 40%);">+ return REF_CLOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ case BDK_CLOCK_RCLK:</span><br><span style="color: hsl(120, 100%, 40%);">+ return thunderx_get_core_clock();</span><br><span style="color: hsl(120, 100%, 40%);">+ case BDK_CLOCK_SCLK:</span><br><span style="color: hsl(120, 100%, 40%);">+ return thunderx_get_io_clock();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span> }</span><br><span> </span><br><span> /**</span><br><span>diff --git a/src/soc/cavium/common/include/soc/clock.h b/src/soc/cavium/common/include/soc/clock.h</span><br><span>new file mode 100644</span><br><span>index 0000000..78025dc</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/cavium/common/include/soc/clock.h</span><br><span>@@ -0,0 +1,15 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPDX-License-Identifier: GPL-2.0+</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u64 thunderx_get_ref_clock(void);</span><br><span style="color: hsl(120, 100%, 40%);">+u64 thunderx_get_io_clock(void);</span><br><span style="color: hsl(120, 100%, 40%);">+u64 thunderx_get_core_clock(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_ */</span><br><span>diff --git a/src/soc/cavium/common/twsi.c b/src/soc/cavium/common/twsi.c</span><br><span>index e2ea838..d9fd3fb 100644</span><br><span>--- a/src/soc/cavium/common/twsi.c</span><br><span>+++ b/src/soc/cavium/common/twsi.c</span><br><span>@@ -6,16 +6,13 @@</span><br><span> </span><br><span> #include <console/console.h></span><br><span> #include <soc/twsi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span> #include <device/i2c.h></span><br><span> #include <device/i2c_simple.h></span><br><span> #include <assert.h></span><br><span> #include <delay.h></span><br><span> #include <arch/io.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_BOOT ((void *const)0x87e006001600ll)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLL_REF_CLK 50000000 /* 50 MHz */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define TWSI_THP 24</span><br><span> </span><br><span> #define TWSI_SW_TWSI 0x1000</span><br><span>@@ -23,32 +20,6 @@</span><br><span> #define TWSI_INT 0x1010</span><br><span> #define TWSI_SW_TWSI_EXT 0x1018</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-union rst_boot {</span><br><span style="color: hsl(0, 100%, 40%);">- u64 u;</span><br><span style="color: hsl(0, 100%, 40%);">- struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u64 rboot_pin:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 rboot:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 lboot:10;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 lboot_ext23:6;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 lboot_ext45:6;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 reserved_24_29:6;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 lboot_oci:3;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 pnr_mul:6;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 reserved_39_39:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 c_mul:7;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 reserved_47_54:8;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 dis_scan:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 dis_huk:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 vrm_err:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 jt_tstmode:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ckill_ppdis:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 trusted_mode:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 ejtagdis:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 jtcsrdis:1;</span><br><span style="color: hsl(0, 100%, 40%);">- u64 chipkill:1;</span><br><span style="color: hsl(0, 100%, 40%);">- } s;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> union twsx_sw_twsi {</span><br><span> u64 u;</span><br><span> struct {</span><br><span>@@ -636,16 +607,14 @@</span><br><span> </span><br><span> static int twsi_set_speed(void *baseaddr, const unsigned int speed)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int io_clock_hz;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 io_clock_hz;</span><br><span> int n_div;</span><br><span> int m_div;</span><br><span> union twsx_sw_twsi sw_twsi;</span><br><span style="color: hsl(0, 100%, 40%);">- union rst_boot rst_boot;</span><br><span> </span><br><span> printk(BIOS_DEBUG, "%s(%p, %u)\n", __func__, baseaddr, speed);</span><br><span style="color: hsl(0, 100%, 40%);">- rst_boot.u = read64(RST_BOOT);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- io_clock_hz = rst_boot.s.pnr_mul * PLL_REF_CLK;</span><br><span style="color: hsl(120, 100%, 40%);">+ io_clock_hz = thunderx_get_io_clock();</span><br><span> </span><br><span> /* Set the TWSI clock to a conservative TWSI_BUS_FREQ. Compute the</span><br><span> * clocks M divider based on the SCLK.</span><br><span>diff --git a/src/soc/cavium/common/wdt.c b/src/soc/cavium/common/wdt.c</span><br><span>index 514a304..9b0f28f 100644</span><br><span>--- a/src/soc/cavium/common/wdt.c</span><br><span>+++ b/src/soc/cavium/common/wdt.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> */</span><br><span> void watchdog_set(unsigned int timeout_ms)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t sclk = clock_get_rate(BDK_CLOCK_SCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t sclk = thunderx_get_io_clock();</span><br><span> uint64_t timeout_sclk = sclk * timeout_ms / 1000;</span><br><span> /* Per comment above, we want the watchdog to expire at 3x the rate specified */</span><br><span> timeout_sclk /= 3;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23752">change 23752</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23752"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifc4fdbaeec78e2fbc956b4821730f2c16f779b91 </div>
<div style="display:none"> Gerrit-Change-Number: 23752 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>