<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23722">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRs<br><br>AMD fixed MTRRs have RdDram and WrDram bits that help route memory<br>accesses to DRAM or MMIO. These are typically hidden for normal<br>operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to<br>BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at<br>reset, should be set for configuration during POST, then cleared for<br>normal operation.<br><br>Attempting to modify the RdDram and WrDram settings without unhiding<br>them causes a General Protection Fault. Add a function to enable or<br>disable MtrrFixDramModEn.<br><br>During commit_fixed_mtrrs() ensure the setting is enabled then<br>disabled after writing the registers.<br><br>In mp_init.c save_bsp_msrs() copies the fixed MTRR settings. Enable<br>the bits so the complete MTRR contents may be read. Restore the<br>setting when complete.<br><br>Finally, modify sipi_vector.S to enable the bits prior to writing<br>the fixed MTRRs and disable when complete.<br><br>BUG=b:68019051<br>TEST=Boot Kahlee, check steps with HDT<br><br>Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/cpu/x86/mp_init.c<br>M src/cpu/x86/mtrr/mtrr.c<br>M src/cpu/x86/sipi_vector.S<br>M src/include/cpu/x86/mtrr.h<br>4 files changed, 50 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/23722/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c</span><br><span>index baa6aec..40349aa 100644</span><br><span>--- a/src/cpu/x86/mp_init.c</span><br><span>+++ b/src/cpu/x86/mp_init.c</span><br><span>@@ -310,6 +310,8 @@</span><br><span> </span><br><span> msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ fixed_mtrrs_hide_rwdram(); /* hide Rd/WrDram bits if supported */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> return msr_count;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c</span><br><span>index c2c629c..a2a04fb 100644</span><br><span>--- a/src/cpu/x86/mtrr/mtrr.c</span><br><span>+++ b/src/cpu/x86/mtrr/mtrr.c</span><br><span>@@ -36,8 +36,8 @@</span><br><span> #include <arch/cpu.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <memrange.h></span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)</span><br><span> #include <cpu/amd/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)</span><br><span> #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)</span><br><span> #else</span><br><span> #define MTRR_FIXED_WRBACK_BITS 0</span><br><span>@@ -83,6 +83,30 @@</span><br><span> wrmsr(MTRR_DEF_TYPE_MSR, msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void fixed_mtrrs_expose_rwdram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t syscfg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ syscfg = rdmsr(SYSCFG_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ syscfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(SYSCFG_MSR, syscfg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void fixed_mtrrs_hide_rwdram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t syscfg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ syscfg = rdmsr(SYSCFG_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ syscfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(SYSCFG_MSR, syscfg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void enable_var_mtrr(unsigned char deftype)</span><br><span> {</span><br><span> msr_t msr;</span><br><span>@@ -310,6 +334,8 @@</span><br><span> msr_t fixed_msrs[NUM_FIXED_MTRRS];</span><br><span> unsigned long msr_index[NUM_FIXED_MTRRS];</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ fixed_mtrrs_expose_rwdram(); /* unhide Rd/WrDram bits if supported */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> memset(&fixed_msrs, 0, sizeof(fixed_msrs));</span><br><span> </span><br><span> msr_num = 0;</span><br><span>diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S</span><br><span>index bd60c65..83606bd 100644</span><br><span>--- a/src/cpu/x86/sipi_vector.S</span><br><span>+++ b/src/cpu/x86/sipi_vector.S</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> </span><br><span> /* The SIPI vector is responsible for initializing the APs in the sytem. It</span><br><span> * loads microcode, sets up MSRs, and enables caching before calling into</span><br><span>@@ -172,6 +173,15 @@</span><br><span> mov msr_count, %ebx</span><br><span> test %ebx, %ebx</span><br><span> jz 1f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Allow modification of RdDram and WrDram bits */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $SYSCFG_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ or $SYSCFG_MSR_MtrrFixDramModEn, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> load_msr:</span><br><span> mov (%edi), %ecx</span><br><span> mov 4(%edi), %eax</span><br><span>@@ -181,6 +191,13 @@</span><br><span> dec %ebx</span><br><span> jnz load_msr</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $SYSCFG_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ and $~SYSCFG_MSR_MtrrFixDramModEn, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> 1:</span><br><span> /* Enable caching. */</span><br><span> mov %cr0, %eax</span><br><span>diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h</span><br><span>index a72d602..bc0f1fe 100644</span><br><span>--- a/src/include/cpu/x86/mtrr.h</span><br><span>+++ b/src/include/cpu/x86/mtrr.h</span><br><span>@@ -76,6 +76,10 @@</span><br><span> */</span><br><span> void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);</span><br><span> void enable_fixed_mtrr(void);</span><br><span style="color: hsl(120, 100%, 40%);">+/* Unhide Rd/WrDram bits in AMD fixed MTRRs and allow modification. */</span><br><span style="color: hsl(120, 100%, 40%);">+void fixed_mtrrs_expose_rwdram(void);</span><br><span style="color: hsl(120, 100%, 40%);">+/* Hide Rd/WrDram bits in AMD fixed MTRRs and prevent modification */</span><br><span style="color: hsl(120, 100%, 40%);">+void fixed_mtrrs_hide_rwdram(void);</span><br><span> void x86_setup_fixed_mtrrs(void);</span><br><span> /* Set up fixed MTRRs but do not enable them. */</span><br><span> void x86_setup_fixed_mtrrs_no_enable(void);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23722">change 23722</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3 </div>
<div style="display:none"> Gerrit-Change-Number: 23722 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>