<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23737">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/scaleway/tagada: Update HSIO configuration<br><br>Change-Id: I213ea13078fdc28489eb4572a084146df333a31d<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/mainboard/scaleway/tagada/hsio.c<br>M src/mainboard/scaleway/tagada/hsio.h<br>2 files changed, 528 insertions(+), 531 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/23737/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c</span><br><span>index fa17130..a8a2035 100644</span><br><span>--- a/src/mainboard/scaleway/tagada/hsio.c</span><br><span>+++ b/src/mainboard/scaleway/tagada/hsio.c</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Online SAS.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -14,23 +14,13 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <harcuvar_boardid.h></span><br><span> #include <hsio.h></span><br><span> #include <soc/fiamux.h></span><br><span> </span><br><span> size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t boardid = board_id();</span><br><span> size_t num;</span><br><span style="color: hsl(0, 100%, 40%);">- switch (boardid) {</span><br><span style="color: hsl(0, 100%, 40%);">- case BoardIdHarcuvar:</span><br><span style="color: hsl(0, 100%, 40%);">- num = ARRAY_SIZE(harcuvar_hsio_config);</span><br><span style="color: hsl(0, 100%, 40%);">- (*p_hsio_config) = (BL_HSIO_INFORMATION *)harcuvar_hsio_config;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- num = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- (*p_hsio_config) = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ num = ARRAY_SIZE(tagada_hsio_config);</span><br><span style="color: hsl(120, 100%, 40%);">+ (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;</span><br><span> return num;</span><br><span> }</span><br><span>diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h</span><br><span>index ce059fd..e49fefd 100644</span><br><span>--- a/src/mainboard/scaleway/tagada/hsio.h</span><br><span>+++ b/src/mainboard/scaleway/tagada/hsio.h</span><br><span>@@ -2,6 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2016-2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -20,605 +21,611 @@</span><br><span> #include <fsp/util.h></span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+const BL_HSIO_INFORMATION tagada_hsio_config[] = {</span><br><span> /*</span><br><span> * Supported Lanes:</span><br><span> * 20</span><br><span> *</span><br><span> * Bifurcation:</span><br><span style="color: hsl(0, 100%, 40%);">- * PCIE cluster #0: x8</span><br><span style="color: hsl(0, 100%, 40%);">- * PCIE cluster #1: x4x4</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCIE cluster #0: x4x4</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCIE cluster #1: x2x2x2x2 (used for M2)</span><br><span> *</span><br><span> * FIA MUX config:</span><br><span style="color: hsl(0, 100%, 40%);">- * Lane[00:07]->x8 PCIE slot</span><br><span style="color: hsl(0, 100%, 40%);">- * Lane[08:11]->a x4 PCIe slot</span><br><span style="color: hsl(0, 100%, 40%);">- * Lane[12:15]->a 2nd x4 PCIe slot</span><br><span style="color: hsl(0, 100%, 40%);">- * Lane[16]->a SATA connector with pin7 to 5V adapter capable</span><br><span style="color: hsl(0, 100%, 40%);">- * Lane[17:18] -> 2 SATA connectors</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lane[00:03]-> disconnected</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lane[08:11]-> 4 SATA side connectors</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lane[12:15]-> 4 PCIe or 2 SATA (12,14) on M2 Connectors.</span><br><span style="color: hsl(120, 100%, 40%);">+ * M2 modules are detected; configuration updated by coreboot</span><br><span> * Lane[19]->USB3 rear I/O panel connector</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */</span><br><span> {BL_SKU_HSIO_20,</span><br><span style="color: hsl(0, 100%, 40%);">- {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4},</span><br><span style="color: hsl(0, 100%, 40%);">- {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE04) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE05) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE06) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_SKU_HSIO_12,</span><br><span> {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(0, 100%, 40%);">- {/*ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span> </span><br><span> /* ME_FIA_SATA_CONFIG */</span><br><span> {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span> </span><br><span> /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span> {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_12,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG( BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */</span><br><span> {BL_SKU_HSIO_10,</span><br><span> {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span> {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_SKU_HSIO_08,</span><br><span style="color: hsl(0, 100%, 40%);">- {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(0, 100%, 40%);">- {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_SKU_HSIO_06,</span><br><span style="color: hsl(0, 100%, 40%);">- {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(0, 100%, 40%);">- {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(0, 100%, 40%);">- {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span> BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span> </span><br><span> /* ME_FIA_SATA_CONFIG */</span><br><span> {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span> BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span> </span><br><span> /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span> {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span> BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- BL_FIA_PCIE_ROOT_PORT_7)} } }</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_08,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_06,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } }</span><br><span> };</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/* _MAINBOARD_HSIO_H */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _MAINBOARD_HSIO_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23737">change 23737</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I213ea13078fdc28489eb4572a084146df333a31d </div>
<div style="display:none"> Gerrit-Change-Number: 23737 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>