<p>Shamile Khan would like Hannah Williams to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/23742">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/glkrvp: Configure eSPI GPIOs to enable S0ix<br><br>Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa<br>Signed-off-by: Hannah Williams <hannah.williams@intel.com><br>Signed-off-by: Shamile Khan <shamile.khan@intel.com><br>---<br>M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c<br>1 file changed, 3 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/23742/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c</span><br><span>index 0646bcf..81d6ba3 100644</span><br><span>--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c</span><br><span>@@ -188,6 +188,9 @@</span><br><span>         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD3*/</span><br><span>       PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1),/*LPC_CLKRUNB*/</span><br><span>      PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_FRAMEB*/</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+      PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*LPC_FRAMEB*/</span><br><span style="color: hsl(120, 100%, 40%);">+     PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 0, DEEP,  NONE, IGNORE, ENPU),/*LPC_CLKRUNB*/</span><br><span> #endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */</span><br><span>    PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/</span><br><span>      PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23742">change 23742</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23742"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa </div>
<div style="display:none"> Gerrit-Change-Number: 23742 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shamile Khan <shamile.khan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>