<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23723">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Use generic fixed MTRR setup<br><br>Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost<br>when stoneyridge was converted from a cpu/northbridge/southbridge<br>implementation to soc/.<br><br>Remove the setup from model_15_init.c because this is duplicated<br>functionality.<br><br>BUG=b:68019051<br>TEST=Boot Kahlee, check steps with HDT<br><br>Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/model_15_init.c<br>2 files changed, 1 insertion(+), 37 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/23723/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig</span><br><span>index 8bf577c..de1cb92 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Kconfig</span><br><span>+++ b/src/soc/amd/stoneyridge/Kconfig</span><br><span>@@ -31,6 +31,7 @@</span><br><span> select ARCH_VERSTAGE_X86_32</span><br><span> select ARCH_ROMSTAGE_X86_32</span><br><span> select ARCH_RAMSTAGE_X86_32</span><br><span style="color: hsl(120, 100%, 40%);">+ select X86_AMD_FIXED_MTRRS</span><br><span> select ACPI_AMD_HARDWARE_SLEEP_VALUES</span><br><span> select COLLECT_TIMESTAMPS_NO_TSC</span><br><span> select DRIVERS_I2C_DESIGNWARE</span><br><span>diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c</span><br><span>index 4bde81e..83fadd0 100644</span><br><span>--- a/src/soc/amd/stoneyridge/model_15_init.c</span><br><span>+++ b/src/soc/amd/stoneyridge/model_15_init.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span> #include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/mtrr.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <string.h></span><br><span>@@ -26,22 +25,9 @@</span><br><span> </span><br><span> #include <cpu/cpu.h></span><br><span> #include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/amdfam15.h></span><br><span> #include <arch/acpi.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void msr_rw_dram(unsigned int reg)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#define RW_DRAM (MTRR_READ_MEM | MTRR_WRITE_MEM)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ALL_RW_DRAM ((RW_DRAM << 24) | (RW_DRAM << 16) | \</span><br><span style="color: hsl(0, 100%, 40%);">- (RW_DRAM << 8) | (RW_DRAM))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t mtrr = rdmsr(reg);</span><br><span style="color: hsl(0, 100%, 40%);">- mtrr.hi |= ALL_RW_DRAM;</span><br><span style="color: hsl(0, 100%, 40%);">- mtrr.lo |= ALL_RW_DRAM;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(reg, mtrr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void model_15_init(device_t dev)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Model 15 Init.\n");</span><br><span>@@ -49,29 +35,6 @@</span><br><span> int i;</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- disable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable access to AMD RdDram and WrDram extension bits */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(SYSCFG_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SYSCFG_MSR, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Send all but A0000-BFFFF to DRAM */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_rw_dram(MTRR_FIX_64K_00000);</span><br><span style="color: hsl(0, 100%, 40%);">- msr_rw_dram(MTRR_FIX_16K_80000);</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = MTRR_FIX_4K_C0000 ; i <= MTRR_FIX_4K_F8000 ; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- msr_rw_dram(i);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Hide RdDram and WrDram bits, and clear Tom2ForceMemTypeWB */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(SYSCFG_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~SYSCFG_MSR_TOM2WB;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= SYSCFG_MSR_MtrrFixDramEn;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SYSCFG_MSR, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- x86_enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* zero the machine check error status registers */</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23723">change 23723</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb </div>
<div style="display:none"> Gerrit-Change-Number: 23723 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>