<p>shkim has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23731">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variant/nautilus: Enable and configure DPTF<br><br>This change enables DPTF and configures the policy.<br>DPTF parameters have been provided by internal power team.<br><br>BUG=b:67877437<br>BRANCH=master<br>TEST=emerge-nautilus coreboot<br><br>Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144<br>---<br>M src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>M src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl<br>2 files changed, 69 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/23731/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>index be8ab5b..9714766 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>@@ -21,6 +21,9 @@</span><br><span> # EC memory map range is 0x900-0x9ff</span><br><span> register "gen3_dec" = "0x00fc0901"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # Enable S0ix</span><br><span> register "s0ix_enable" = "1"</span><br><span> </span><br><span>diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl</span><br><span>index 216b76f..12cb1e0 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl</span><br><span>+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl</span><br><span>@@ -1,7 +1,8 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -9,8 +10,70 @@</span><br><span> *</span><br><span> * This program is distributed in the hope that it will be useful,</span><br><span> * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Dummy file until DPTF support is added. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 105</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_ID 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_NAME "Charger"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_PASSIVE 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_CRITICAL 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_TABLET_PASSIVE 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_TABLET_CRITICAL 90</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_ID 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_NAME "DRAM"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_PASSIVE 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_CRITICAL 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_TABLET_PASSIVE 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_TABLET_CRITICAL 90</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Charger performance states, board-specific values from charger and EC */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (CHPS, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DTRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Charger Throttle Effect on Charger (TSR0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on DRAM (TSR1) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MPPC, Package ()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x2, /* Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 7000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 5000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 5000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 200 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Include DPTF */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/skylake/acpi/dptf/dptf.asl></span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23731">change 23731</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144 </div>
<div style="display:none"> Gerrit-Change-Number: 23731 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: shkim <sh_.kim@samsung.com> </div>