<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23717">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">device/ddr2,ddr3: Rename and move a few things<br><br>In order for ddr2.h and ddr3.h to be included in the same file it<br>cannot have conflicting definitions, therefore rename a few things and<br>move some things to a common header.<br><br>Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/device/dram/ddr2.c<br>A src/include/device/dram/common.h<br>M src/include/device/dram/ddr2.h<br>M src/include/device/dram/ddr3.h<br>M src/northbridge/intel/i945/raminit.c<br>M src/northbridge/intel/x4x/raminit.c<br>6 files changed, 100 insertions(+), 101 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/23717/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c</span><br><span>index 0117b93..eefb569 100644</span><br><span>--- a/src/device/dram/ddr2.c</span><br><span>+++ b/src/device/dram/ddr2.c</span><br><span>@@ -38,11 +38,11 @@</span><br><span> *</span><br><span> * @param type DIMM type. This is byte[20] of the SPD.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-int spd_dimm_is_registered_ddr2(enum spd_dimm_type type)</span><br><span style="color: hsl(120, 100%, 40%);">+int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if ((type == SPD_DIMM_TYPE_RDIMM)</span><br><span style="color: hsl(0, 100%, 40%);">- || (type == SPD_DIMM_TYPE_72B_SO_RDIMM)</span><br><span style="color: hsl(0, 100%, 40%);">- || (type == SPD_DIMM_TYPE_MINI_RDIMM))</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((type == SPD_DDR2_DIMM_TYPE_RDIMM)</span><br><span style="color: hsl(120, 100%, 40%);">+ || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM)</span><br><span style="color: hsl(120, 100%, 40%);">+ || (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))</span><br><span> return 1;</span><br><span> </span><br><span> return 0;</span><br><span>@@ -297,7 +297,7 @@</span><br><span> * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was</span><br><span> * detected.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])</span><br><span style="color: hsl(120, 100%, 40%);">+int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])</span><br><span> {</span><br><span> u8 spd_size, cl, reg8;</span><br><span> u16 eeprom_size;</span><br><span>@@ -582,7 +582,7 @@</span><br><span> }</span><br><span> printram("\n");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ dimm->dimm_type = spd[20] & SPD_DDR2_DIMM_TYPE_MASK;</span><br><span> printram(" Dimm type : %x\n", dimm->dimm_type);</span><br><span> </span><br><span> dimm->flags.is_ecc = !!(spd[11] & 0x3);</span><br><span>@@ -648,7 +648,7 @@</span><br><span> *</span><br><span> * @param dimm pointer to already decoded @ref dimm_attr structure</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-void dram_print_spd_ddr2(const struct dimm_attr_st *dimm)</span><br><span style="color: hsl(120, 100%, 40%);">+void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm)</span><br><span> {</span><br><span> char buf[32];</span><br><span> int i;</span><br><span>diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h</span><br><span>new file mode 100644</span><br><span>index 0000000..4702370</span><br><span>--- /dev/null</span><br><span>+++ b/src/include/device/dram/common.h</span><br><span>@@ -0,0 +1,70 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DEVICE_DRAM_COMMON_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEVICE_DRAM_COMMON_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief Convenience definitions for TCK values</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Different values for tCK, representing standard DDR3 frequencies.</span><br><span style="color: hsl(120, 100%, 40%);">+ * These values are in 1/256 ns units.</span><br><span style="color: hsl(120, 100%, 40%);">+ * @{</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NS2MHZ_DIV256 (1000 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_1333MHZ 192</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_1200MHZ 212</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_1100MHZ 232</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_1066MHZ 240</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_1000MHZ 256</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_933MHZ 274</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_900MHZ 284</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_800MHZ 320</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_700MHZ 365</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_666MHZ 384</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_533MHZ 480</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_400MHZ 640</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_333MHZ 768</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_266MHZ 960</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCK_200MHZ 1280</span><br><span style="color: hsl(120, 100%, 40%);">+/** @} */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Use this macro instead of printk(); for verbose RAM initialization messages.</span><br><span style="color: hsl(120, 100%, 40%);">+ * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically</span><br><span style="color: hsl(120, 100%, 40%);">+ * disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ * @{</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)</span><br><span style="color: hsl(120, 100%, 40%);">+#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define printram(x, ...)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+/** @} */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Result of the SPD decoding process */</span><br><span style="color: hsl(120, 100%, 40%);">+enum spd_status {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_STATUS_OK = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_STATUS_INVALID,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_STATUS_CRC_ERROR,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_STATUS_INVALID_FIELD,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* DEVICE_DRAM_COMMON_H */</span><br><span>diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h</span><br><span>index 7322b12..4aad1bc 100644</span><br><span>--- a/src/include/device/dram/ddr2.h</span><br><span>+++ b/src/include/device/dram/ddr2.h</span><br><span>@@ -30,55 +30,24 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <spd.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * \brief Convenience definitions for TCK values</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Different values for tCK, representing standard DDR2 frequencies.</span><br><span style="color: hsl(0, 100%, 40%);">- * These values are in 1/256 ns units.</span><br><span style="color: hsl(0, 100%, 40%);">- * @{</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_800MHZ 320</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_700MHZ 365</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_666MHZ 384</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_533MHZ 480</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_400MHZ 640</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_333MHZ 768</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_266MHZ 960</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_200MHZ 1280</span><br><span style="color: hsl(0, 100%, 40%);">-/** @} */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Use this macro instead of printk(); for verbose RAM initialization messages.</span><br><span style="color: hsl(0, 100%, 40%);">- * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically</span><br><span style="color: hsl(0, 100%, 40%);">- * disabled.</span><br><span style="color: hsl(0, 100%, 40%);">- * @{</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)</span><br><span style="color: hsl(0, 100%, 40%);">-#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define printram(x, ...)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/** @} */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/dram/common.h></span><br><span> </span><br><span> /*</span><br><span> * Module type (byte 20, bits 5:0) of SPD</span><br><span> * This definition is specific to DDR2. DDR3 SPDs have a different structure.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-enum spd_dimm_type {</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_UNDEFINED = 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_RDIMM = 0x01,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_UDIMM = 0x02,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_SO_DIMM = 0x04,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_MICRO_DIMM = 0x08,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_MINI_RDIMM = 0x10,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_MINI_UDIMM = 0x20,</span><br><span style="color: hsl(120, 100%, 40%);">+enum spd_dimm_type_ddr2 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_RDIMM = 0x01,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_UDIMM = 0x02,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_72B_SO_CDIMM = 0x06,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM = 0x07,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_MICRO_DIMM = 0x08,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_MINI_RDIMM = 0x10,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_MINI_UDIMM = 0x20,</span><br><span> /* Masks to bits 5:0 to give the dimm type */</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_DIMM_TYPE_MASK = 0x3f,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DDR2_DIMM_TYPE_MASK = 0x3f,</span><br><span> };</span><br><span> </span><br><span> /**</span><br><span>@@ -86,7 +55,7 @@</span><br><span> *</span><br><span> * Characteristic flags for the DIMM, as presented by the SPD</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-union dimm_flags_st {</span><br><span style="color: hsl(120, 100%, 40%);">+union dimm_flags_ddr2_st {</span><br><span> /* The whole point of the union/struct construct is to allow us to clear</span><br><span> * all the bits with one line: flags.raw = 0.</span><br><span> * We do not care how these bits are ordered */</span><br><span>@@ -130,9 +99,9 @@</span><br><span> *</span><br><span> * The characteristics of each DIMM, as presented by the SPD</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-struct dimm_attr_st {</span><br><span style="color: hsl(120, 100%, 40%);">+struct dimm_attr_ddr2_st {</span><br><span> enum spd_memory_type dram_type;</span><br><span style="color: hsl(0, 100%, 40%);">- enum spd_dimm_type dimm_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ enum spd_dimm_type_ddr2 dimm_type;</span><br><span> /* BCD SPD revision */</span><br><span> u8 rev;</span><br><span> /* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */</span><br><span>@@ -144,7 +113,7 @@</span><br><span> * Fields 0 and 1 are unused. */</span><br><span> u32 access_time[8];</span><br><span> /* Flags extracted from SPD */</span><br><span style="color: hsl(0, 100%, 40%);">- union dimm_flags_st flags;</span><br><span style="color: hsl(120, 100%, 40%);">+ union dimm_flags_ddr2_st flags;</span><br><span> /* Number of banks */</span><br><span> u8 banks;</span><br><span> /* SDRAM width */</span><br><span>@@ -199,23 +168,15 @@</span><br><span> u32 serial;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Result of the SPD decoding process */</span><br><span style="color: hsl(0, 100%, 40%);">-enum spd_status {</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_OK = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_INVALID,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_CRC_ERROR,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_INVALID_FIELD,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /** Maximum SPD size supported */</span><br><span> #define SPD_SIZE_MAX_DDR2 128</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-int spd_dimm_is_registered_ddr2(enum spd_dimm_type type);</span><br><span style="color: hsl(120, 100%, 40%);">+int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type);</span><br><span> u8 spd_ddr2_calc_checksum(u8 *spd, int len);</span><br><span> u32 spd_decode_spd_size_ddr2(u8 byte0);</span><br><span> u32 spd_decode_eeprom_size_ddr2(u8 byte1);</span><br><span style="color: hsl(0, 100%, 40%);">-int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);</span><br><span style="color: hsl(0, 100%, 40%);">-void dram_print_spd_ddr2(const struct dimm_attr_st *dimm);</span><br><span style="color: hsl(120, 100%, 40%);">+int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);</span><br><span style="color: hsl(120, 100%, 40%);">+void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm);</span><br><span> void normalize_tck(u32 *tclk);</span><br><span> u8 spd_get_msbs(u8 c);</span><br><span> </span><br><span>diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h</span><br><span>index 2cfd6ac..0756095 100644</span><br><span>--- a/src/include/device/dram/ddr3.h</span><br><span>+++ b/src/include/device/dram/ddr3.h</span><br><span>@@ -31,6 +31,8 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <spd.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/dram/common.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> /**</span><br><span> * Convenience definitions for SPD offsets</span><br><span>@@ -46,32 +48,6 @@</span><br><span> /** @} */</span><br><span> </span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * \brief Convenience definitions for TCK values</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Different values for tCK, representing standard DDR3 frequencies.</span><br><span style="color: hsl(0, 100%, 40%);">- * These values are in 1/256 ns units.</span><br><span style="color: hsl(0, 100%, 40%);">- * @{</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define NS2MHZ_DIV256 (1000 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_1333MHZ 192</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_1200MHZ 212</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_1100MHZ 232</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_1066MHZ 240</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_1000MHZ 256</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_933MHZ 274</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_900MHZ 284</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_800MHZ 320</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_700MHZ 365</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_666MHZ 384</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_533MHZ 480</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_400MHZ 640</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_333MHZ 768</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_266MHZ 960</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCK_200MHZ 1280</span><br><span style="color: hsl(0, 100%, 40%);">-/** @} */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span> * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP</span><br><span> *</span><br><span> * Use this macro instead of printk(); for verbose RAM initialization messages.</span><br><span>@@ -198,14 +174,6 @@</span><br><span> u8 part_number[17];</span><br><span> } dimm_attr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Result of the SPD decoding process */</span><br><span style="color: hsl(0, 100%, 40%);">-enum spd_status {</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_OK = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_INVALID,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_CRC_ERROR,</span><br><span style="color: hsl(0, 100%, 40%);">- SPD_STATUS_INVALID_FIELD,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> enum ddr3_xmp_profile {</span><br><span> DDR3_XMP_PROFILE_1 = 0,</span><br><span> DDR3_XMP_PROFILE_2 = 1,</span><br><span>diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c</span><br><span>index b350b67..b2348f5 100644</span><br><span>--- a/src/northbridge/intel/i945/raminit.c</span><br><span>+++ b/src/northbridge/intel/i945/raminit.c</span><br><span>@@ -362,7 +362,7 @@</span><br><span> </span><br><span> for (i = 0; i < (2 * DIMM_SOCKETS); i++) {</span><br><span> int device = get_dimm_spd_address(sysinfo, i), bytes_read;</span><br><span style="color: hsl(0, 100%, 40%);">- struct dimm_attr_st dimm_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dimm_attr_ddr2_st dimm_info;</span><br><span> </span><br><span> /* Initialize the socket information with a sane value */</span><br><span> sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;</span><br><span>diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c</span><br><span>index cd786bb..7bb5f2b 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,</span><br><span> struct abs_timings *saved_timings, struct sysinfo *s)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- struct dimm_attr_st decoded_dimm;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dimm_attr_ddr2_st decoded_dimm;</span><br><span> int i;</span><br><span> </span><br><span> if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23717">change 23717</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6 </div>
<div style="display:none"> Gerrit-Change-Number: 23717 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>