<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23713">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">driver/uart: Reintroduce default_baudrate as weak function.<br><br>The rationale is to allow the mainboard to override the default<br>baudrate for instance by sampling GPIOs at boot.<br><br>This partially reverts the commit named<br>"mb/*/*: Remove rtc nvram configurable baud rate"<br>commit b29078e4015bbc3e8cf00ba64f0799c087546563.<br><br>Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/cpu/allwinner/a10/uart.c<br>M src/cpu/allwinner/a10/uart_console.c<br>M src/cpu/ti/am335x/uart.c<br>M src/drivers/uart/pl011.c<br>M src/drivers/uart/uart8250io.c<br>M src/drivers/uart/uart8250mem.c<br>M src/drivers/uart/util.c<br>M src/include/console/uart.h<br>M src/soc/broadcom/cygnus/ns16550.c<br>M src/soc/imgtec/pistachio/uart.c<br>M src/soc/mediatek/mt8173/uart.c<br>M src/soc/nvidia/tegra124/uart.c<br>M src/soc/nvidia/tegra210/uart.c<br>M src/soc/qualcomm/ipq40xx/uart.c<br>M src/soc/samsung/exynos5250/uart.c<br>M src/soc/samsung/exynos5420/uart.c<br>16 files changed, 35 insertions(+), 19 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/23713/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c</span><br><span>index f7c2db9..45dcaed 100644</span><br><span>--- a/src/cpu/allwinner/a10/uart.c</span><br><span>+++ b/src/cpu/allwinner/a10/uart.c</span><br><span>@@ -105,7 +105,7 @@</span><br><span> struct a10_uart *uart_base = uart_platform_baseptr(idx);</span><br><span> </span><br><span> /* Use default 8N1 encoding */</span><br><span style="color: hsl(0, 100%, 40%);">- a10_uart_configure(uart_base, CONFIG_TTYS0_BAUD,</span><br><span style="color: hsl(120, 100%, 40%);">+ a10_uart_configure(uart_base, default_baudrate(),</span><br><span> 8, UART_PARITY_NONE, 1);</span><br><span> a10_uart_enable_fifos(uart_base);</span><br><span> }</span><br><span>diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c</span><br><span>index 03d4122..e7774c9 100644</span><br><span>--- a/src/cpu/allwinner/a10/uart_console.c</span><br><span>+++ b/src/cpu/allwinner/a10/uart_console.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 1;</span><br><span> serial.input_hertz = uart_platform_refclk();</span><br><span> serial.uart_pci_addr = 0;</span><br><span>diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c</span><br><span>index 47b9a3d..45a693a 100644</span><br><span>--- a/src/cpu/ti/am335x/uart.c</span><br><span>+++ b/src/cpu/ti/am335x/uart.c</span><br><span>@@ -163,7 +163,7 @@</span><br><span> {</span><br><span> struct am335x_uart *uart = uart_platform_baseptr(idx);</span><br><span> uint16_t div = (uint16_t) uart_baudrate_divisor(</span><br><span style="color: hsl(0, 100%, 40%);">- CONFIG_TTYS0_BAUD, uart_platform_refclk(), 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ default_baudrate(), uart_platform_refclk(), 16);</span><br><span> am335x_uart_init(uart, div);</span><br><span> }</span><br><span> </span><br><span>@@ -189,7 +189,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 2;</span><br><span> lb_add_serial(&serial, data);</span><br><span> </span><br><span>diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c</span><br><span>index 709320b..0c7ac08 100644</span><br><span>--- a/src/drivers/uart/pl011.c</span><br><span>+++ b/src/drivers/uart/pl011.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 1;</span><br><span> serial.input_hertz = uart_platform_refclk();</span><br><span> serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;</span><br><span>diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c</span><br><span>index ace2c59..4cc7fe3 100644</span><br><span>--- a/src/drivers/uart/uart8250io.c</span><br><span>+++ b/src/drivers/uart/uart8250io.c</span><br><span>@@ -107,7 +107,7 @@</span><br><span> {</span><br><span> if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250IO_SKIP_INIT)) {</span><br><span> unsigned int div;</span><br><span style="color: hsl(0, 100%, 40%);">- div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,</span><br><span style="color: hsl(120, 100%, 40%);">+ div = uart_baudrate_divisor(default_baudrate(),</span><br><span> uart_platform_refclk(), uart_input_clock_divider());</span><br><span> uart8250_init(uart_platform_base(idx), div);</span><br><span> }</span><br><span>@@ -134,7 +134,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_IO_MAPPED;</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 1;</span><br><span> serial.input_hertz = uart_platform_refclk();</span><br><span> serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;</span><br><span>diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c</span><br><span>index 9eb50cb..5a1e366 100644</span><br><span>--- a/src/drivers/uart/uart8250mem.c</span><br><span>+++ b/src/drivers/uart/uart8250mem.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> return;</span><br><span> </span><br><span> unsigned int div;</span><br><span style="color: hsl(0, 100%, 40%);">- div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,</span><br><span style="color: hsl(120, 100%, 40%);">+ div = uart_baudrate_divisor(default_baudrate(),</span><br><span> uart_platform_refclk(), uart_input_clock_divider());</span><br><span> uart8250_mem_init(base, div);</span><br><span> }</span><br><span>@@ -156,7 +156,7 @@</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span> if (!serial.baseaddr)</span><br><span> return;</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))</span><br><span> serial.regwidth = sizeof(uint32_t);</span><br><span> else</span><br><span>diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c</span><br><span>index c7b9ab2..9f9b01b 100644</span><br><span>--- a/src/drivers/uart/util.c</span><br><span>+++ b/src/drivers/uart/util.c</span><br><span>@@ -14,6 +14,17 @@</span><br><span> #include <console/console.h></span><br><span> #include <console/uart.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_BAUDRATE 115200</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) unsigned int default_baudrate(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * If TTYS0_BAUD is not configured, then by default use 115200 as the</span><br><span style="color: hsl(120, 100%, 40%);">+ * baud rate.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ return CONFIG_TTYS0_BAUD ? CONFIG_TTYS0_BAUD : DEFAULT_BAUDRATE;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Calculate divisor. Do not floor but round to nearest integer. */</span><br><span> unsigned int uart_baudrate_divisor(unsigned int baudrate,</span><br><span> unsigned int refclk, unsigned int oversample)</span><br><span>diff --git a/src/include/console/uart.h b/src/include/console/uart.h</span><br><span>index 0dccd00..e2df893 100644</span><br><span>--- a/src/include/console/uart.h</span><br><span>+++ b/src/include/console/uart.h</span><br><span>@@ -23,6 +23,11 @@</span><br><span> * baudrate generator. */</span><br><span> unsigned int uart_platform_refclk(void);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the baudrate, defaults to CONFIG_TTYS0_BAUD.</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function is weak and can be overridden by mainboard if needed.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned int default_baudrate(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Returns the divisor value for a given baudrate.</span><br><span> * The formula to satisfy is:</span><br><span> * refclk / divisor = baudrate * oversample</span><br><span>diff --git a/src/soc/broadcom/cygnus/ns16550.c b/src/soc/broadcom/cygnus/ns16550.c</span><br><span>index e700827..aa9dd2d 100644</span><br><span>--- a/src/soc/broadcom/cygnus/ns16550.c</span><br><span>+++ b/src/soc/broadcom/cygnus/ns16550.c</span><br><span>@@ -120,7 +120,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = (uintptr_t)regs;</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 4;</span><br><span> lb_add_serial(&serial, data);</span><br><span> </span><br><span>diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c</span><br><span>index df1a5ac..1f39e8b 100644</span><br><span>--- a/src/soc/imgtec/pistachio/uart.c</span><br><span>+++ b/src/soc/imgtec/pistachio/uart.c</span><br><span>@@ -150,7 +150,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 1 << UART_SHIFT;</span><br><span> lb_add_serial(&serial, data);</span><br><span> </span><br><span>diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c</span><br><span>index 36a279f..d0b140d 100644</span><br><span>--- a/src/soc/mediatek/mt8173/uart.c</span><br><span>+++ b/src/soc/mediatek/mt8173/uart.c</span><br><span>@@ -177,7 +177,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = UART0_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 4;</span><br><span> lb_add_serial(&serial, data);</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c</span><br><span>index 0d52337..76ea426 100644</span><br><span>--- a/src/soc/nvidia/tegra124/uart.c</span><br><span>+++ b/src/soc/nvidia/tegra124/uart.c</span><br><span>@@ -136,7 +136,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 4;</span><br><span> lb_add_serial(&serial, data);</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c</span><br><span>index 1c52687..608b443 100644</span><br><span>--- a/src/soc/nvidia/tegra210/uart.c</span><br><span>+++ b/src/soc/nvidia/tegra210/uart.c</span><br><span>@@ -123,7 +123,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 4;</span><br><span> lb_add_serial(&serial, data);</span><br><span> </span><br><span>diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c</span><br><span>index 671a6d1..2ea390b 100644</span><br><span>--- a/src/soc/qualcomm/ipq40xx/uart.c</span><br><span>+++ b/src/soc/qualcomm/ipq40xx/uart.c</span><br><span>@@ -297,7 +297,7 @@</span><br><span> </span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = (uint32_t)UART1_DM_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 1;</span><br><span> </span><br><span> lb_add_serial(&serial, data);</span><br><span>diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c</span><br><span>index 7ad6cbe..07f1e34 100644</span><br><span>--- a/src/soc/samsung/exynos5250/uart.c</span><br><span>+++ b/src/soc/samsung/exynos5250/uart.c</span><br><span>@@ -61,7 +61,7 @@</span><br><span> </span><br><span> // All UARTs share the same clock.</span><br><span> uclk = clock_get_periph_rate(PERIPH_ID_UART3);</span><br><span style="color: hsl(0, 100%, 40%);">- val = uclk / CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ val = uclk / default_baudrate();</span><br><span> </span><br><span> write32(&uart->ubrdiv, val / 16 - 1);</span><br><span> </span><br><span>@@ -191,7 +191,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 4;</span><br><span> lb_add_serial(&serial, data);</span><br><span> </span><br><span>diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c</span><br><span>index a38be07..6f54c00 100644</span><br><span>--- a/src/soc/samsung/exynos5420/uart.c</span><br><span>+++ b/src/soc/samsung/exynos5420/uart.c</span><br><span>@@ -61,7 +61,7 @@</span><br><span> </span><br><span> // All UARTs share the same clock.</span><br><span> uclk = clock_get_periph_rate(PERIPH_ID_UART3);</span><br><span style="color: hsl(0, 100%, 40%);">- val = uclk / CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ val = uclk / default_baudrate();</span><br><span> </span><br><span> write32(&uart->ubrdiv, val / 16 - 1);</span><br><span> </span><br><span>@@ -182,7 +182,7 @@</span><br><span> struct lb_serial serial;</span><br><span> serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;</span><br><span> serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(0, 100%, 40%);">- serial.baud = CONFIG_TTYS0_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial.baud = default_baudrate();</span><br><span> serial.regwidth = 4;</span><br><span> serial.input_hertz = uart_platform_refclk();</span><br><span> serial.uart_pci_addr = 0;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23713">change 23713</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23713"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc </div>
<div style="display:none"> Gerrit-Change-Number: 23713 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>