<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23719">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/cannonlake_rvp: Enable SAR function<br><br>Change-Id: I23fc4d519376b2079bf95ae496903728adfdca96<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/Kconfig<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>2 files changed, 12 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23719/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig</span><br><span>index fb6f9b1..622a2eb 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/Kconfig</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig</span><br><span>@@ -79,4 +79,10 @@</span><br><span> config VBOOT</span><br><span>  select VBOOT_LID_SWITCH</span><br><span>      select VBOOT_MOCK_SECDATA</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+  select DSAR_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+    select SAR_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+     select USE_SAR</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>index 8502048..1e39253 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>@@ -77,7 +77,12 @@</span><br><span>              device pci 12.6 off end # GSPI #2</span><br><span>            device pci 14.0 on  end # USB xHCI</span><br><span>           device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(0, 100%, 40%);">-                device pci 14.3 on  end # CNVi wifi</span><br><span style="color: hsl(120, 100%, 40%);">+           device pci 14.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+                    chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+                               register "wake" = "GPE0_PME_B0"</span><br><span style="color: hsl(120, 100%, 40%);">+                           device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+                        end</span><br><span style="color: hsl(120, 100%, 40%);">+           end # CNVi wifi</span><br><span>              device pci 14.5 on  end # SDCard</span><br><span>             device pci 15.0 on</span><br><span>                   chip drivers/i2c/hid</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23719">change 23719</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23719"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I23fc4d519376b2079bf95ae496903728adfdca96 </div>
<div style="display:none"> Gerrit-Change-Number: 23719 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>