<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23698">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Add generic PCR asl<br><br>Access to PCH Private Configuration Space Register can be addressed via<br>SBERG_BAR, the method is generic across several generations of Intel<br>SOC.<br><br>BUG=None<br>TEST=None<br><br>Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>A src/soc/intel/common/acpi/pcr.asl<br>1 file changed, 90 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/23698/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/acpi/pcr.asl b/src/soc/intel/common/acpi/pcr.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..9dc77e2</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/acpi/pcr.asl</span><br><span>@@ -0,0 +1,90 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Calculate PCR register base at specified PID</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - PCR Port ID</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (PCRB, 1, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Add (CONFIG_PCR_BASE_ADDRESS,</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (Arg0, PCR_PORTID_SHIFT)))</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Read a PCR register at specified PID and offset</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - PCR Port ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg1 - Register Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (PCRR, 2, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (PCRD, DWordAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DATA, 32</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (DATA)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * AND a value with PCR register at specified PID and offset</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - PCR Port ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg1 - Register Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg2 - Value to AND</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (PCRA, 3, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (PCRD, DWordAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DATA, 32</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ And (DATA, Arg2, DATA)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * After every write one needs to read an innocuous register</span><br><span style="color: hsl(120, 100%, 40%);">+ * to ensure the writes are completed for certain ports. This is done</span><br><span style="color: hsl(120, 100%, 40%);">+ * for all ports so that the callers don't need the per-port knowledge</span><br><span style="color: hsl(120, 100%, 40%);">+ * for each transaction.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCRR (Arg0, Arg1)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * OR a value with PCR register at specified PID and offset</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg0 - PCR Port ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg1 - Register Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ * Arg2 - Value to OR</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (PCRO, 3, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (PCRD, DWordAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DATA, 32</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Or (DATA, Arg2, DATA)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * After every write one needs to read an innocuous register</span><br><span style="color: hsl(120, 100%, 40%);">+ * to ensure the writes are completed for certain ports. This is done</span><br><span style="color: hsl(120, 100%, 40%);">+ * for all ports so that the callers don't need the per-port knowledge</span><br><span style="color: hsl(120, 100%, 40%);">+ * for each transaction.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCRR (Arg0, Arg1)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23698">change 23698</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23698"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026 </div>
<div style="display:none"> Gerrit-Change-Number: 23698 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>