<p>Youness Alaoui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23683">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">purism/librem_skl: Enable TPM support<br><br>Change the GPIO to match the TPM-enabled motherboards, and add TPM<br>support in devicetree and enable the config.<br>After changing the GPIO table, the librem 13v2 and librem 15v3 now<br>have the same GPIOs, so use a single gpio.h file instead of one<br>file per variant.<br><br>Change-Id: I425654c1c972118aa81c27961246238c2eef782d<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>---<br>M src/mainboard/purism/librem_skl/Kconfig<br>M src/mainboard/purism/librem_skl/Makefile.inc<br>R src/mainboard/purism/librem_skl/gpio.h<br>M src/mainboard/purism/librem_skl/ramstage.c<br>M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb<br>M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb<br>D src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h<br>7 files changed, 16 insertions(+), 211 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/23683/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig</span><br><span>index f68fd23..be4b7a3 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/Kconfig</span><br><span>+++ b/src/mainboard/purism/librem_skl/Kconfig</span><br><span>@@ -9,6 +9,7 @@</span><br><span> select SERIRQ_CONTINUOUS_MODE</span><br><span> select MAINBOARD_USES_FSP2_0</span><br><span> select SPD_READ_BY_WORD</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LPC_TPM</span><br><span> </span><br><span> if BOARD_PURISM_BASEBOARD_LIBREM_SKL</span><br><span> </span><br><span>diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc</span><br><span>index 18c9ad6..eb01360 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/Makefile.inc</span><br><span>+++ b/src/mainboard/purism/librem_skl/Makefile.inc</span><br><span>@@ -19,4 +19,3 @@</span><br><span> ramstage-y += ramstage.c</span><br><span> ramstage-y += hda_verb.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/include/variant/gpio.h b/src/mainboard/purism/librem_skl/gpio.h</span><br><span>similarity index 93%</span><br><span>rename from src/mainboard/purism/librem_skl/variants/librem13v2/include/variant/gpio.h</span><br><span>rename to src/mainboard/purism/librem_skl/gpio.h</span><br><span>index 148e40b..e3328a3 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem13v2/include/variant/gpio.h</span><br><span>+++ b/src/mainboard/purism/librem_skl/gpio.h</span><br><span>@@ -41,9 +41,9 @@</span><br><span> /* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),</span><br><span> /* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),</span><br><span> /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A18, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A20, NONE, DEEP),</span><br><span> /* ISH_GP3 */ PAD_CFG_NC(GPP_A21),</span><br><span> /* ISH_GP4 */ PAD_CFG_NC(GPP_A22),</span><br><span> /* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span>@@ -108,18 +108,18 @@</span><br><span> /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),</span><br><span> /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span> /* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),</span><br><span> /* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),</span><br><span> /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),</span><br><span> /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span> /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),</span><br><span> /* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),</span><br><span> /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1),</span><br><span> /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1),</span><br><span> /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),</span><br><span> /* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),</span><br><span> /* I2S_MCLK */ PAD_CFG_NC(GPP_D23),</span><br><span>diff --git a/src/mainboard/purism/librem_skl/ramstage.c b/src/mainboard/purism/librem_skl/ramstage.c</span><br><span>index 15912cf..94f8071 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/ramstage.c</span><br><span>+++ b/src/mainboard/purism/librem_skl/ramstage.c</span><br><span>@@ -15,7 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <soc/ramstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "gpio.h"</span><br><span> </span><br><span> void mainboard_silicon_init_params(FSP_SIL_UPD *params)</span><br><span> {</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>index 1fc19a5..e2e2ac0 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>@@ -195,6 +195,9 @@</span><br><span> chip ec/purism/librem</span><br><span> device pnp 0c09.0 on end</span><br><span> end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span> end # LPC Interface</span><br><span> device pci 1f.1 on end # P2SB</span><br><span> device pci 1f.2 on end # Power Management Controller</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>index 647f054..6cf183a 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>@@ -202,6 +202,9 @@</span><br><span> chip ec/purism/librem</span><br><span> device pnp 0c09.0 on end</span><br><span> end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span> end # LPC Interface</span><br><span> device pci 1f.1 on end # P2SB</span><br><span> device pci 1f.2 on end # Power Management Controller</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h b/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h</span><br><span>deleted file mode 100644</span><br><span>index 9c22f00..0000000</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem15v3/include/variant/gpio.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,201 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MAINBOARD_GPIO_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_GPIO_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpe.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Pad configuration in ramstage. */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PIRQA# */ PAD_CFG_NC(GPP_A7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PME# */ PAD_CFG_NC(GPP_A11),</span><br><span style="color: hsl(0, 100%, 40%);">-/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* VRALERT# */ PAD_CFG_NC(GPP_B2),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RXD */ PAD_CFG_NC(GPP_C12),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_TXD */ PAD_CFG_NC(GPP_C13),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RTS# */ PAD_CFG_NC(GPP_C14),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_CTS# */ PAD_CFG_NC(GPP_C15),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RXD */ PAD_CFG_NC(GPP_C20),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_TXD */ PAD_CFG_NC(GPP_C21),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RTS# */ PAD_CFG_NC(GPP_C22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_CTS# */ PAD_CFG_NC(GPP_C23),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),</span><br><span style="color: hsl(0, 100%, 40%);">-/* FASHTRIG */ PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATALED# */ PAD_CFG_NC(GPP_E8),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SDA */ PAD_CFG_NC(GPP_F10),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */ PAD_CFG_NC(GPP_F23),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* BATLOW# */ PAD_CFG_NC(GPD0),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAN_WAKE# */ PAD_CFG_NC(GPD2),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23683">change 23683</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I425654c1c972118aa81c27961246238c2eef782d </div>
<div style="display:none"> Gerrit-Change-Number: 23683 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>