<p>Justin TerAvest has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23679">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">DRAFT: Normalize GPIO initialization on kahlee.<br><br>This makes the flow for GPIO initialization more closely folllow that<br>for other boards.<br><br>Note: This will probably break gardenia so this can't go in as is, but<br>I'm curious about comments on the strategy here.<br><br>Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d<br>Signed-off-by: Justin TerAvest <teravest@chromium.org><br>---<br>M src/mainboard/google/kahlee/Makefile.inc<br>M src/mainboard/google/kahlee/bootblock/bootblock.c<br>A src/mainboard/google/kahlee/ramstage.c<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>M src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/chip.c<br>A src/soc/amd/stoneyridge/include/soc/ramstage.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>11 files changed, 86 insertions(+), 26 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23679/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc</span><br><span>index 770a999..514373e 100644</span><br><span>--- a/src/mainboard/google/kahlee/Makefile.inc</span><br><span>+++ b/src/mainboard/google/kahlee/Makefile.inc</span><br><span>@@ -25,6 +25,7 @@</span><br><span> ramstage-y += chromeos.c</span><br><span> ramstage-y += ec.c</span><br><span> ramstage-y += OemCustomize.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ramstage.c</span><br><span> </span><br><span> verstage-y += chromeos.c</span><br><span> verstage-y += ec.c</span><br><span>diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>index 90c8acb..244abe0 100644</span><br><span>--- a/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>@@ -13,12 +13,18 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span> #include <bootblock_common.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <variant/ec.h></span><br><span> </span><br><span> void bootblock_mainboard_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_stoneyridge_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpios = variant_early_gpio_table(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_program_gpios(gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Enable the EC as soon as we have visibility */</span><br><span> mainboard_ec_init();</span><br><span> </span><br><span>diff --git a/src/mainboard/google/kahlee/ramstage.c b/src/mainboard/google/kahlee/ramstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7fdf495</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/kahlee/ramstage.c</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/southbridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void ramstage_mainboard_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_stoneyridge_gpio *gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpios = variant_gpio_table(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_program_gpios(gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>index a6bcea5..8d90174 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>@@ -258,13 +258,14 @@</span><br><span> { GPIO_135, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio</span><br><span style="color: hsl(0, 100%, 40%);">- *board_get_gpio(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if (GPIO_TABLE_BOOTBLOCK) {</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_reset;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage_reset;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span> return gpio_set_stage_ram;</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>index bf14ef4..5bbc11d 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -26,5 +26,7 @@</span><br><span> int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);</span><br><span> int variant_get_xhci_oc_map(uint16_t *usb_oc_map);</span><br><span> int variant_get_ehci_oc_map(uint16_t *usb_oc_map);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size);</span><br><span> </span><br><span> #endif /* __BASEBOARD_VARIANTS_H__ */</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>index e357c7e..d1cc017 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>@@ -96,12 +96,14 @@</span><br><span> {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if (GPIO_TABLE_BOOTBLOCK) {</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_reset;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage_reset;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span> *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span> return gpio_set_stage_ram;</span><br><span> }</span><br><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index 709b413..3eff5eb 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -125,8 +125,6 @@</span><br><span> post_code(0x37);</span><br><span> do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- sb_program_gpio();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> post_code(0x38);</span><br><span> /* APs will not exit amdinitearly */</span><br><span> do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly");</span><br><span>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c</span><br><span>index d3a8bc4..bd48c74 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.c</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.c</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/northbridge.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <amdblocks/psp.h></span><br><span> #include <amdblocks/agesawrapper.h></span><br><span>@@ -89,9 +90,16 @@</span><br><span> dev->ops = &stoneyridge_i2c_mmio_ops;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Mainboard GPIO configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) void ramstage_mainboard_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void soc_init(void *chip_info)</span><br><span> {</span><br><span> southbridge_init(chip_info);</span><br><span style="color: hsl(120, 100%, 40%);">+ ramstage_mainboard_init();</span><br><span> setup_bsp_ramtop();</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/ramstage.h b/src/soc/amd/stoneyridge/include/soc/ramstage.h</span><br><span>new file mode 100644</span><br><span>index 0000000..014c48b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/ramstage.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_RAMSTAGE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_RAMSTAGE_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void ramstage_mainboard_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index f4d6b17..259e8b5 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -350,9 +350,13 @@</span><br><span> /**</span><br><span> * @brief program a particular set of GPIO</span><br><span> *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param gpio_ptr = pointer to array of gpio configurations</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param size = number of entries in array</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span> * @return none</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-void sb_program_gpio(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr,</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t size);</span><br><span> /**</span><br><span> * @brief Find the size of a particular wide IO</span><br><span> *</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 735642f..a14213f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -155,15 +155,13 @@</span><br><span> return irq_association;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sb_program_gpio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr,</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t size)</span><br><span> {</span><br><span> void *tmp_ptr;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct soc_amd_stoneyridge_gpio *gpio_ptr;</span><br><span style="color: hsl(0, 100%, 40%);">- size_t size;</span><br><span> uint8_t control, mux, index;</span><br><span> </span><br><span> printk(BIOS_SPEW, "GPIO programming stage %s\n", STR_GPIO_STAGE);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_ptr = board_get_gpio(&size);</span><br><span> for (index = 0; index < size; index++) {</span><br><span> mux = gpio_ptr[index].function;</span><br><span> control = gpio_ptr[index].control;</span><br><span>@@ -181,14 +179,6 @@</span><br><span> printk(BIOS_SPEW, "End GPIO programming\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb_program_gpio_ram(void *unused)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- sb_program_gpio();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,</span><br><span style="color: hsl(0, 100%, 40%);">- sb_program_gpio_ram, NULL);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /**</span><br><span> * @brief Find the size of a particular wide IO</span><br><span> *</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23679">change 23679</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d </div>
<div style="display:none"> Gerrit-Change-Number: 23679 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Justin TerAvest <teravest@chromium.org> </div>