<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23669">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/haswell: Get rid off device_t<br><br>Use of `device_t` has been<br>abandoned in ramstage<br><br>Change-Id: Ica914a76f4638621e12441adb29731ab078d8bee<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/haswell/acpi.c<br>M src/northbridge/intel/haswell/gma.c<br>M src/northbridge/intel/haswell/minihd.c<br>M src/northbridge/intel/haswell/northbridge.c<br>4 files changed, 19 insertions(+), 19 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/23669/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c</span><br><span>index e032948..d8ac4e2 100644</span><br><span>--- a/src/northbridge/intel/haswell/acpi.c</span><br><span>+++ b/src/northbridge/intel/haswell/acpi.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> </span><br><span> unsigned long acpi_fill_mcfg(unsigned long current)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  u32 pciexbar = 0;</span><br><span>    u32 pciexbar_reg;</span><br><span>    int max_buses;</span><br><span>diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c</span><br><span>index c7319fb..3a348d2 100644</span><br><span>--- a/src/northbridge/intel/haswell/gma.c</span><br><span>+++ b/src/northbridge/intel/haswell/gma.c</span><br><span>@@ -487,7 +487,7 @@</span><br><span>        intel_gma_restore_opregion();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -501,7 +501,7 @@</span><br><span> const struct i915_gpu_controller_info *</span><br><span> intel_gma_get_controller_info(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));</span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));</span><br><span>     if (!dev) {</span><br><span>          return NULL;</span><br><span>         }</span><br><span>@@ -509,7 +509,7 @@</span><br><span>      return &chip->gfx;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_ssdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gma_ssdt(struct device *device)</span><br><span> {</span><br><span>    const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();</span><br><span>        if (!gfx) {</span><br><span>diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c</span><br><span>index 9e7ce0e..6c528da 100644</span><br><span>--- a/src/northbridge/intel/haswell/minihd.c</span><br><span>+++ b/src/northbridge/intel/haswell/minihd.c</span><br><span>@@ -103,7 +103,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void minihd_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void minihd_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>      if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c</span><br><span>index 32be916..68cc647 100644</span><br><span>--- a/src/northbridge/intel/haswell/northbridge.c</span><br><span>+++ b/src/northbridge/intel/haswell/northbridge.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span> #include "chip.h"</span><br><span> #include "haswell.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)</span><br><span style="color: hsl(120, 100%, 40%);">+static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)</span><br><span> {</span><br><span>  u32 pciexbar_reg;</span><br><span>    u32 mask;</span><br><span>@@ -69,7 +69,7 @@</span><br><span>        return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span>  assign_resources(dev->link_list);</span><br><span> }</span><br><span>@@ -87,7 +87,7 @@</span><br><span>        .ops_pci_bus      = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)</span><br><span style="color: hsl(120, 100%, 40%);">+static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)</span><br><span> {</span><br><span>    u32 bar;</span><br><span> </span><br><span>@@ -106,7 +106,7 @@</span><br><span> /* There are special BARs that actually are programmed in the MCHBAR. These</span><br><span>  * Intel special features, but they do consume resources that need to be</span><br><span>  * accounted for. */</span><br><span style="color: hsl(0, 100%, 40%);">-static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *len)</span><br><span style="color: hsl(120, 100%, 40%);">+static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)</span><br><span> {</span><br><span>     u32 bar;</span><br><span> </span><br><span>@@ -125,7 +125,7 @@</span><br><span> struct fixed_mmio_descriptor {</span><br><span>         unsigned int index;</span><br><span>  u32 size;</span><br><span style="color: hsl(0, 100%, 40%);">-       int (*get_resource)(device_t dev, unsigned int index,</span><br><span style="color: hsl(120, 100%, 40%);">+ int (*get_resource)(struct device *dev, unsigned int index,</span><br><span>                      u32 *base, u32 *size);</span><br><span>   const char *description;</span><br><span> };</span><br><span>@@ -145,7 +145,7 @@</span><br><span>  * Add all known fixed MMIO ranges that hang off the host bridge/memory</span><br><span>  * controller device.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_add_fixed_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_add_fixed_mmio_resources(struct device *dev)</span><br><span> {</span><br><span>       int i;</span><br><span> </span><br><span>@@ -202,7 +202,7 @@</span><br><span>     const char *description;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void read_map_entry(device_t dev, struct map_entry *entry, uint64_t *result)</span><br><span style="color: hsl(120, 100%, 40%);">+static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result)</span><br><span> {</span><br><span>        uint64_t value;</span><br><span>      uint64_t mask;</span><br><span>@@ -270,7 +270,7 @@</span><br><span>         [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_read_map_entries(device_t dev, uint64_t *values)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_read_map_entries(struct device *dev, uint64_t *values)</span><br><span> {</span><br><span>       int i;</span><br><span>       for (i = 0; i < NUM_MAP_ENTRIES; i++) {</span><br><span>@@ -278,7 +278,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_report_map_entries(device_t dev, uint64_t *values)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_report_map_entries(struct device *dev, uint64_t *values)</span><br><span> {</span><br><span>    int i;</span><br><span>       for (i = 0; i < NUM_MAP_ENTRIES; i++) {</span><br><span>@@ -289,7 +289,7 @@</span><br><span>     printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_add_dram_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_add_dram_resources(struct device *dev)</span><br><span> {</span><br><span>        unsigned long base_k, size_k;</span><br><span>        unsigned long touud_k;</span><br><span>@@ -381,7 +381,7 @@</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_read_resources(struct device *dev)</span><br><span> {</span><br><span>   /* Read standard PCI resources. */</span><br><span>   pci_dev_read_resources(dev);</span><br><span>@@ -393,7 +393,7 @@</span><br><span>   mc_add_dram_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>      if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -457,7 +457,7 @@</span><br><span>       .device = PCI_DEVICE_ID_HSW_ULT,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_bus_init(struct device *dev)</span><br><span> {</span><br><span>  bsp_init_and_start_aps(dev->link_list);</span><br><span> }</span><br><span>@@ -470,7 +470,7 @@</span><br><span>        .scan_bus         = 0,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span>        /* Set the operations if it is a special bus type */</span><br><span>         if (dev->path.type == DEVICE_PATH_DOMAIN) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23669">change 23669</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23669"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ica914a76f4638621e12441adb29731ab078d8bee </div>
<div style="display:none"> Gerrit-Change-Number: 23669 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>