<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23671">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/fsp_rangeley: Get rid off device_t<br><br>Use of `device_t` has been<br>abandoned in ramstage<br><br>Change-Id: I0b969a5109276d108e6140bad338c74786b967f3<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/fsp_rangeley/acpi.c<br>M src/northbridge/intel/fsp_rangeley/northbridge.c<br>M src/northbridge/intel/fsp_rangeley/northbridge.h<br>3 files changed, 12 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/23671/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c</span><br><span>index 00947aa..c8e6d45 100644</span><br><span>--- a/src/northbridge/intel/fsp_rangeley/acpi.c</span><br><span>+++ b/src/northbridge/intel/fsp_rangeley/acpi.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> </span><br><span> unsigned long acpi_fill_mcfg(unsigned long current)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  u32 pciexbar = 0;</span><br><span>    u32 pciexbar_reg;</span><br><span>    int max_buses;</span><br><span>@@ -61,7 +61,7 @@</span><br><span>   return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void northbridge_acpi_fill_ssdt_generator(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void northbridge_acpi_fill_ssdt_generator(struct device *device)</span><br><span> {</span><br><span>    u32 bmbound;</span><br><span>         char pscope[] = "\\_SB.PCI0";</span><br><span>diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>index 0134eff..22e6cee 100644</span><br><span>--- a/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c</span><br><span>@@ -59,7 +59,7 @@</span><br><span> </span><br><span> static int get_pcie_bar(u32 *base)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  u32 pciexbar_reg;</span><br><span> </span><br><span>        *base = 0;</span><br><span>@@ -94,7 +94,7 @@</span><br><span>       return index;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_add_dram_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_add_dram_resources(struct device *dev)</span><br><span> {</span><br><span>    u32 tomlow, bmbound, bsmmrrl, bsmmrrh;</span><br><span>       u64 bmbound_hi;</span><br><span>@@ -139,7 +139,7 @@</span><br><span>        index = add_fixed_resources(dev, index);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_read_resources(struct device *dev)</span><br><span> {</span><br><span>         u32 pcie_config_base;</span><br><span>        int buses;</span><br><span>@@ -158,7 +158,7 @@</span><br><span>     mc_add_dram_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span>        /*</span><br><span>    * Assign memory resources for PCI devices</span><br><span>@@ -168,13 +168,13 @@</span><br><span>   assign_resources(dev->link_list);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_set_resources(struct device *dev)</span><br><span> {</span><br><span>       /* Call the normal set_resources */</span><br><span>  pci_dev_set_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>      if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -189,7 +189,7 @@</span><br><span> {</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void northbridge_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void northbridge_enable(struct device *dev)</span><br><span> {</span><br><span> }</span><br><span> </span><br><span>@@ -239,7 +239,7 @@</span><br><span>     .devices = pci_device_ids,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_bus_init(struct device *dev)</span><br><span> {</span><br><span>        initialize_cpus(dev->link_list);</span><br><span> }</span><br><span>@@ -252,7 +252,7 @@</span><br><span>       .scan_bus         = 0,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span>        /* Set the operations if it is a special bus type */</span><br><span>         if (dev->path.type == DEVICE_PATH_DOMAIN) {</span><br><span>diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h</span><br><span>index ba4cfdd..f68d175 100644</span><br><span>--- a/src/northbridge/intel/fsp_rangeley/northbridge.h</span><br><span>+++ b/src/northbridge/intel/fsp_rangeley/northbridge.h</span><br><span>@@ -73,7 +73,7 @@</span><br><span> void report_platform_info(void);</span><br><span> </span><br><span> #ifndef __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-void northbridge_acpi_fill_ssdt_generator(device_t device);</span><br><span style="color: hsl(120, 100%, 40%);">+void northbridge_acpi_fill_ssdt_generator(struct device *device);</span><br><span> #endif</span><br><span> </span><br><span> #endif /* #ifndef __ASSEMBLER__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23671">change 23671</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23671"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0b969a5109276d108e6140bad338c74786b967f3 </div>
<div style="display:none"> Gerrit-Change-Number: 23671 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>