<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23654">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Get rid off device_t<br><br>Use of `device_t`has been abandoned in ramstage<br><br>Change-Id: I2cc938958097e416b85f6592cb8a4e645a3746ed<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/i945/acpi.c<br>M src/northbridge/intel/i945/gma.c<br>M src/northbridge/intel/i945/northbridge.c<br>3 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/23654/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c</span><br><span>index c1a3d17..990d3de 100644</span><br><span>--- a/src/northbridge/intel/i945/acpi.c</span><br><span>+++ b/src/northbridge/intel/i945/acpi.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> unsigned long acpi_fill_mcfg(unsigned long current)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-     device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  u32 pciexbar = 0;</span><br><span>    u32 pciexbar_reg;</span><br><span>    int max_buses;</span><br><span>diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c</span><br><span>index 8d60bc9..da9c1e2 100644</span><br><span>--- a/src/northbridge/intel/i945/gma.c</span><br><span>+++ b/src/northbridge/intel/i945/gma.c</span><br><span>@@ -739,7 +739,7 @@</span><br><span>            pci_write_config8(dev, 0xf4, 0xff);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_set_subsystem(device_t dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void gma_set_subsystem(struct device *dev, unsigned int vendor,</span><br><span>                         unsigned int device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>@@ -763,7 +763,7 @@</span><br><span>      return &chip->gfx;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_ssdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gma_ssdt(struct device *device)</span><br><span> {</span><br><span>    const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();</span><br><span>        if (!gfx)</span><br><span>@@ -772,7 +772,7 @@</span><br><span>      drivers_intel_gma_displays_ssdt_generate(gfx);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gma_func0_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gma_func0_read_resources(struct device *dev)</span><br><span> {</span><br><span>     u8 reg8;</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c</span><br><span>index fdb37b1..794c61e 100644</span><br><span>--- a/src/northbridge/intel/i945/northbridge.c</span><br><span>+++ b/src/northbridge/intel/i945/northbridge.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span> </span><br><span> static int get_pcie_bar(u32 *base)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  u32 pciexbar_reg;</span><br><span> </span><br><span>        *base = 0;</span><br><span>@@ -57,7 +57,7 @@</span><br><span>       return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span>  uint32_t pci_tolm;</span><br><span>   uint8_t tolud, reg8;</span><br><span>@@ -149,7 +149,7 @@</span><br><span>   .ops_pci_bus      = pci_bus_default_ops,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void mc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void mc_read_resources(struct device *dev)</span><br><span> {</span><br><span>        u32 pcie_config_base;</span><br><span>        int buses;</span><br><span>@@ -163,7 +163,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_set_subsystem(device_t dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_set_subsystem(struct device *dev, unsigned int vendor,</span><br><span>                               unsigned int device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>@@ -199,7 +199,7 @@</span><br><span>      .devices = pci_device_ids,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_bus_init(struct device *dev)</span><br><span> {</span><br><span>        initialize_cpus(dev->link_list);</span><br><span> }</span><br><span>@@ -212,7 +212,7 @@</span><br><span>       .scan_bus         = 0,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span>        /* Set the operations if it is a special bus type */</span><br><span>         if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23654">change 23654</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23654"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2cc938958097e416b85f6592cb8a4e645a3746ed </div>
<div style="display:none"> Gerrit-Change-Number: 23654 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>