<p>Chris Ching has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23626">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Add tis_plat_irq_status<br><br>For variants that have a cr50 tpm, this enables faster polling when<br>interacting with the tpm.<br><br>BUG=b:72838769<br>BRANCH=none<br>TEST=verified on grunt that irq is used and not timeouts for tpm<br><br>Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428<br>Signed-off-by: Chris Ching <chingcodes@chromium.org><br>---<br>M src/mainboard/google/kahlee/bootblock/bootblock.c<br>M src/mainboard/google/kahlee/variants/baseboard/Makefile.inc<br>A src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c<br>M src/soc/amd/stoneyridge/Makefile.inc<br>4 files changed, 34 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/23626/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>index 90c8acb..2fcf674 100644</span><br><span>--- a/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <variant/ec.h></span><br><span> </span><br><span>@@ -24,4 +25,10 @@</span><br><span> </span><br><span> /* Setup TPM decode before verstage */</span><br><span> sb_tpm_decode_spi();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW |</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INT_STATUS_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_config(GPIO_9, flags);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc</span><br><span>index fcaf365..7213b7a 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc</span><br><span>@@ -16,7 +16,10 @@</span><br><span> bootblock-y += gpio.c</span><br><span> bootblock-y += OemCustomize.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += tpm_tis.c</span><br><span> romstage-y += gpio.c</span><br><span> romstage-y += memory.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += tpm_tis.c</span><br><span> </span><br><span> ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += tpm_tis.c</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c</span><br><span>new file mode 100644</span><br><span>index 0000000..2ed391a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/tpm/tis.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int tis_plat_irq_status(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_interrupt_status(GPIO_9);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>index 59405de..d006d5f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>+++ b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>@@ -40,6 +40,7 @@</span><br><span> bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c</span><br><span> bootblock-y += BiosCallOuts.c</span><br><span> bootblock-y += bootblock/bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span> bootblock-y += i2c.c</span><br><span> bootblock-y += monotonic_timer.c</span><br><span> bootblock-y += pmutil.c</span><br><span>@@ -66,6 +67,7 @@</span><br><span> romstage-y += tsc_freq.c</span><br><span> romstage-y += southbridge.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += gpio.c</span><br><span> verstage-y += i2c.c</span><br><span> verstage-y += monotonic_timer.c</span><br><span> verstage-y += sb_util.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23626">change 23626</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 </div>
<div style="display:none"> Gerrit-Change-Number: 23626 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Chris Ching <chingcodes@chromium.org> </div>