<p>Robert Reeves has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23628">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/hp: Add HP Elitebook 8770w<br><br>This is based on the code from the 8470p port. Tested on the quad core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics cards. Tested working with both Quadro K3000M and GTX 980M 8GB.<br><br>Tested and working:<br>- memory: 4G+4G+4G+4G<br>- Linux (Debian Stretch with kernel 4.9.0) boot from SeaBIOS payload with graphics init disabled in coreboot. I allow SeaBIOS to load the VBIOS from the MXM.<br>- WLAN<br>- keyboard, trackpoint and touchpad<br>- USB<br>- serial port on dock<br>- fan control<br>- VGA<br>- Displayport<br>- Audio<br>- S3 with SeaBIOS 1.10.3, not working with 1.11<br>- Brightness and volume FN keys<br><br>Change-Id: I70477cfa314ed607b41b9096bc1b8664eff6baf0<br>Signed-off-by: xiinc37 <xiinc37@gmail.com><br>---<br>M src/mainboard/hp/8770w/Kconfig<br>M src/mainboard/hp/8770w/board_info.txt<br>M src/mainboard/hp/8770w/cmos.layout<br>M src/mainboard/hp/8770w/devicetree.cb<br>D src/mainboard/hp/8770w/gma-mainboard.ads<br>M src/mainboard/hp/8770w/gpio.c<br>M src/mainboard/hp/8770w/hda_verb.c<br>M src/mainboard/hp/8770w/mainboard.c<br>M src/mainboard/hp/8770w/romstage.c<br>9 files changed, 59 insertions(+), 151 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/23628/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig</span><br><span>index 2157867..c650309 100644</span><br><span>--- a/src/mainboard/hp/8770w/Kconfig</span><br><span>+++ b/src/mainboard/hp/8770w/Kconfig</span><br><span>@@ -2,6 +2,7 @@</span><br><span> # This file is part of the coreboot project.</span><br><span> #</span><br><span> # Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Robert Reeves</span><br><span> #</span><br><span> # This program is free software; you can redistribute it and/or modify</span><br><span> # it under the terms of the GNU General Public License as published by</span><br><span>@@ -13,7 +14,7 @@</span><br><span> # GNU General Public License for more details.</span><br><span> #</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_HP_8470P</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_HP_8770W</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span> def_bool y</span><br><span>@@ -23,13 +24,10 @@</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select INTEL_INT15</span><br><span> select NORTHBRIDGE_INTEL_IVYBRIDGE</span><br><span style="color: hsl(0, 100%, 40%);">- select SANDYBRIDGE_IVYBRIDGE_LVDS</span><br><span> select SERIRQ_CONTINUOUS_MODE</span><br><span> select SOUTHBRIDGE_INTEL_C216</span><br><span> select SYSTEM_TYPE_LAPTOP</span><br><span> select USE_NATIVE_RAMINIT</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_LIBGFXINIT</span><br><span style="color: hsl(0, 100%, 40%);">- select GFX_GMA_INTERNAL_IS_LVDS</span><br><span> select EC_HP_KBC1126</span><br><span> select SUPERIO_SMSC_LPC47N217</span><br><span> select HAVE_OPTION_TABLE</span><br><span>@@ -45,23 +43,15 @@</span><br><span> </span><br><span> config MAINBOARD_DIR</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default hp/8470p</span><br><span style="color: hsl(120, 100%, 40%);">+ default hp/8770w</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "EliteBook 8470p"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config VGA_BIOS_FILE</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "pci8086,0166.rom"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config VGA_BIOS_ID</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "8086,0166"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "EliteBook 8770w"</span><br><span> </span><br><span> config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span> hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x176c</span><br><span> </span><br><span> config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span> hex</span><br><span>diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt</span><br><span>index 1d0ca8b..0d04ad0 100644</span><br><span>--- a/src/mainboard/hp/8770w/board_info.txt</span><br><span>+++ b/src/mainboard/hp/8770w/board_info.txt</span><br><span>@@ -1,5 +1,5 @@</span><br><span> Category: laptop</span><br><span style="color: hsl(0, 100%, 40%);">-Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/5257511</span><br><span> ROM protocol: SPI</span><br><span> ROM package: SOIC-16</span><br><span> ROM socketed: n</span><br><span>diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout</span><br><span>index f55fbd5..69d2767 100644</span><br><span>--- a/src/mainboard/hp/8770w/cmos.layout</span><br><span>+++ b/src/mainboard/hp/8770w/cmos.layout</span><br><span>@@ -3,6 +3,7 @@</span><br><span> ##</span><br><span> ## Copyright (C) 2007-2008 coresystems GmbH</span><br><span> ## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Robert Reeves</span><br><span> ##</span><br><span> ## This program is free software; you can redistribute it and/or modify</span><br><span> ## it under the terms of the GNU General Public License as published by</span><br><span>@@ -64,7 +65,6 @@</span><br><span> #424 8 r 0 unused</span><br><span> </span><br><span> # coreboot config options: northbridge</span><br><span style="color: hsl(0, 100%, 40%);">-432 3 e 11 gfx_uma_size</span><br><span> #435 5 r 0 unused</span><br><span> </span><br><span> 440 8 h 0 volume</span><br><span>@@ -88,27 +88,20 @@</span><br><span> 2 1 Disable</span><br><span> 4 0 Fallback</span><br><span> 4 1 Normal</span><br><span style="color: hsl(0, 100%, 40%);">-6 0 Emergency</span><br><span style="color: hsl(0, 100%, 40%);">-6 1 Alert</span><br><span style="color: hsl(0, 100%, 40%);">-6 2 Critical</span><br><span style="color: hsl(0, 100%, 40%);">-6 3 Error</span><br><span style="color: hsl(0, 100%, 40%);">-6 4 Warning</span><br><span style="color: hsl(0, 100%, 40%);">-6 5 Notice</span><br><span style="color: hsl(0, 100%, 40%);">-6 6 Info</span><br><span style="color: hsl(0, 100%, 40%);">-6 7 Debug</span><br><span style="color: hsl(0, 100%, 40%);">-6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 9 Spew</span><br><span> 7 0 Disable</span><br><span> 7 1 Enable</span><br><span> 7 2 Keep</span><br><span> 9 0 AHCI</span><br><span> 9 1 Compatible</span><br><span style="color: hsl(0, 100%, 40%);">-11 0 32M</span><br><span style="color: hsl(0, 100%, 40%);">-11 1 64M</span><br><span style="color: hsl(0, 100%, 40%);">-11 2 96M</span><br><span style="color: hsl(0, 100%, 40%);">-11 3 128M</span><br><span style="color: hsl(0, 100%, 40%);">-11 4 160M</span><br><span style="color: hsl(0, 100%, 40%);">-11 5 192M</span><br><span style="color: hsl(0, 100%, 40%);">-11 6 224M</span><br><span> </span><br><span> # -----------------------------------------------------------------</span><br><span> checksums</span><br><span>diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb</span><br><span>index b7254bb..2f2a5e0 100644</span><br><span>--- a/src/mainboard/hp/8770w/devicetree.cb</span><br><span>+++ b/src/mainboard/hp/8770w/devicetree.cb</span><br><span>@@ -2,6 +2,7 @@</span><br><span> # This file is part of the coreboot project.</span><br><span> #</span><br><span> # Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Robert Reeves</span><br><span> #</span><br><span> # This program is free software; you can redistribute it and/or modify</span><br><span> # it under the terms of the GNU General Public License as published by</span><br><span>@@ -15,21 +16,6 @@</span><br><span> #</span><br><span> </span><br><span> chip northbridge/intel/sandybridge</span><br><span style="color: hsl(0, 100%, 40%);">- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gfx.link_frequency_270_mhz" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gfx.ndid" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gfx.use_spread_spectrum_clock" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_cpu_backlight" = "0x00000385"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_dp_b_hotplug" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_dp_c_hotplug" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_dp_d_hotplug" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_panel_port_select" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_panel_power_backlight_off_delay" = "2000"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_panel_power_backlight_on_delay" = "2000"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_panel_power_cycle_delay" = "5"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_panel_power_down_delay" = "230"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_panel_power_up_delay" = "300"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gpu_pch_backlight" = "0x0d9c0d9c"</span><br><span> device cpu_cluster 0x0 on</span><br><span> chip cpu/intel/socket_rPGA989</span><br><span> device lapic 0x0 on</span><br><span>@@ -48,15 +34,15 @@</span><br><span> end</span><br><span> device domain 0x0 on</span><br><span> device pci 00.0 on # Host bridge</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 01.0 on # PCIe Bridge for discrete graphics</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 02.0 on # Internal graphics VGA controller</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 off # Internal graphics VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH</span><br><span> register "c2_latency" = "0x0065"</span><br><span> register "docking_supported" = "0"</span><br><span> register "gen1_dec" = "0x007c0201"</span><br><span>@@ -68,7 +54,7 @@</span><br><span> register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"</span><br><span> register "pcie_port_coalesce" = "1"</span><br><span> register "sata_interface_speed_support" = "0x3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "sata_port_map" = "0x3b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x1f"</span><br><span> register "superspeed_capable_ports" = "0x0000000f"</span><br><span> register "xhci_overcurrent_mapping" = "0x00000c03"</span><br><span> register "xhci_switchable_ports" = "0x0000000f"</span><br><span>@@ -77,40 +63,40 @@</span><br><span> register "spi_lvscc" = "0"</span><br><span> </span><br><span> device pci 14.0 on # USB 3.0 Controller</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 16.0 on # Management Engine Interface 1</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 16.1 off # Management Engine Interface 2</span><br><span> end</span><br><span> device pci 16.2 off # Management Engine IDE-R</span><br><span> end</span><br><span> device pci 16.3 on # Management Engine KT</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 19.0 on # Intel Gigabit Ethernet</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 1a.0 on # USB2 EHCI #2</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 1b.0 on # High Definition Audio Audio controller</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 1c.0 on # PCIe Port #1</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.1 on # PCIe Port #2, ExpressCard</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.2 on # PCIe Port #3, SD/MMC</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.3 on # PCIe Port #4, WLAN</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.4 off # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on # PCIe Port #5</span><br><span> end</span><br><span> device pci 1c.5 off # PCIe Port #6</span><br><span> end</span><br><span>@@ -119,12 +105,12 @@</span><br><span> device pci 1c.7 off # PCIe Port #8</span><br><span> end</span><br><span> device pci 1d.0 on # USB2 EHCI #1</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 1e.0 off # PCI bridge</span><br><span> end</span><br><span> device pci 1f.0 on # LPC bridge PCI-LPC bridge</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> chip ec/hp/kbc1126</span><br><span> register "ec_data_port" = "0x62"</span><br><span> register "ec_cmd_port" = "0x66"</span><br><span>@@ -146,7 +132,7 @@</span><br><span> end #chip superio/smsc/lpc47n217</span><br><span> end</span><br><span> device pci 1f.2 on # SATA Controller 1</span><br><span style="color: hsl(0, 100%, 40%);">- subsystemid 0x103c 0x179b</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span> end</span><br><span> device pci 1f.3 off # SMBus</span><br><span> end</span><br><span>diff --git a/src/mainboard/hp/8770w/gma-mainboard.ads b/src/mainboard/hp/8770w/gma-mainboard.ads</span><br><span>deleted file mode 100644</span><br><span>index da495f6..0000000</span><br><span>--- a/src/mainboard/hp/8770w/gma-mainboard.ads</span><br><span>+++ /dev/null</span><br><span>@@ -1,34 +0,0 @@</span><br><span>---</span><br><span>--- Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span>---</span><br><span>--- This program is free software; you can redistribute it and/or modify</span><br><span>--- it under the terms of the GNU General Public License as published by</span><br><span>--- the Free Software Foundation; either version 2 of the License, or</span><br><span>--- (at your option) any later version.</span><br><span>---</span><br><span>--- This program is distributed in the hope that it will be useful,</span><br><span>--- but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span>--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span>--- GNU General Public License for more details.</span><br><span>---</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-with HW.GFX.GMA;</span><br><span style="color: hsl(0, 100%, 40%);">-with HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-use HW.GFX.GMA;</span><br><span style="color: hsl(0, 100%, 40%);">-use HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-private package GMA.Mainboard is</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- ports : constant Port_List :=</span><br><span style="color: hsl(0, 100%, 40%);">- (DP1,</span><br><span style="color: hsl(0, 100%, 40%);">- DP2,</span><br><span style="color: hsl(0, 100%, 40%);">- DP3,</span><br><span style="color: hsl(0, 100%, 40%);">- HDMI1,</span><br><span style="color: hsl(0, 100%, 40%);">- HDMI2,</span><br><span style="color: hsl(0, 100%, 40%);">- HDMI3,</span><br><span style="color: hsl(0, 100%, 40%);">- Analog,</span><br><span style="color: hsl(0, 100%, 40%);">- Internal,</span><br><span style="color: hsl(0, 100%, 40%);">- others => Disabled);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-end GMA.Mainboard;</span><br><span>diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c</span><br><span>index 768af5c..ac054d9 100644</span><br><span>--- a/src/mainboard/hp/8770w/gpio.c</span><br><span>+++ b/src/mainboard/hp/8770w/gpio.c</span><br><span>@@ -3,6 +3,7 @@</span><br><span> *</span><br><span> * Copyright (C) 2008-2009 coresystems GmbH</span><br><span> * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or</span><br><span> * modify it under the terms of the GNU General Public License as</span><br><span>@@ -18,7 +19,7 @@</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> </span><br><span> static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_NATIVE,</span><br><span> .gpio1 = GPIO_MODE_GPIO,</span><br><span> .gpio2 = GPIO_MODE_GPIO,</span><br><span> .gpio3 = GPIO_MODE_GPIO,</span><br><span>@@ -32,28 +33,27 @@</span><br><span> .gpio11 = GPIO_MODE_GPIO,</span><br><span> .gpio12 = GPIO_MODE_NATIVE,</span><br><span> .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio14 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span> .gpio15 = GPIO_MODE_GPIO,</span><br><span> .gpio16 = GPIO_MODE_GPIO,</span><br><span> .gpio17 = GPIO_MODE_GPIO,</span><br><span> .gpio18 = GPIO_MODE_NATIVE,</span><br><span> .gpio19 = GPIO_MODE_NATIVE,</span><br><span> .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_NATIVE,</span><br><span> .gpio22 = GPIO_MODE_GPIO,</span><br><span> .gpio23 = GPIO_MODE_GPIO,</span><br><span> .gpio24 = GPIO_MODE_GPIO,</span><br><span> .gpio25 = GPIO_MODE_NATIVE,</span><br><span> .gpio26 = GPIO_MODE_NATIVE,</span><br><span> .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_NATIVE,</span><br><span> .gpio29 = GPIO_MODE_GPIO,</span><br><span> .gpio30 = GPIO_MODE_NATIVE,</span><br><span> .gpio31 = GPIO_MODE_NATIVE,</span><br><span> };</span><br><span> </span><br><span> static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio0 = GPIO_DIR_OUTPUT,</span><br><span> .gpio1 = GPIO_DIR_INPUT,</span><br><span> .gpio2 = GPIO_DIR_OUTPUT,</span><br><span> .gpio3 = GPIO_DIR_INPUT,</span><br><span>@@ -64,29 +64,23 @@</span><br><span> .gpio10 = GPIO_DIR_INPUT,</span><br><span> .gpio11 = GPIO_DIR_OUTPUT,</span><br><span> .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio14 = GPIO_DIR_INPUT,</span><br><span> .gpio15 = GPIO_DIR_INPUT,</span><br><span> .gpio16 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio17 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span> .gpio22 = GPIO_DIR_OUTPUT,</span><br><span> .gpio23 = GPIO_DIR_INPUT,</span><br><span> .gpio24 = GPIO_DIR_OUTPUT,</span><br><span> .gpio27 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio28 = GPIO_DIR_OUTPUT,</span><br><span> .gpio29 = GPIO_DIR_OUTPUT,</span><br><span> };</span><br><span> </span><br><span> static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio0 = GPIO_LEVEL_LOW,</span><br><span> .gpio2 = GPIO_LEVEL_LOW,</span><br><span> .gpio8 = GPIO_LEVEL_LOW,</span><br><span> .gpio11 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio17 = GPIO_LEVEL_HIGH,</span><br><span> .gpio22 = GPIO_LEVEL_HIGH,</span><br><span> .gpio24 = GPIO_LEVEL_HIGH,</span><br><span> .gpio27 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio28 = GPIO_LEVEL_LOW,</span><br><span> .gpio29 = GPIO_LEVEL_HIGH,</span><br><span> };</span><br><span> </span><br><span>@@ -102,7 +96,6 @@</span><br><span> .gpio7 = GPIO_INVERT,</span><br><span> .gpio10 = GPIO_INVERT,</span><br><span> .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio14 = GPIO_INVERT,</span><br><span> };</span><br><span> </span><br><span> static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span>@@ -112,9 +105,9 @@</span><br><span> .gpio32 = GPIO_MODE_NATIVE,</span><br><span> .gpio33 = GPIO_MODE_GPIO,</span><br><span> .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_NATIVE,</span><br><span> .gpio38 = GPIO_MODE_GPIO,</span><br><span> .gpio39 = GPIO_MODE_GPIO,</span><br><span> .gpio40 = GPIO_MODE_NATIVE,</span><br><span>@@ -126,7 +119,7 @@</span><br><span> .gpio46 = GPIO_MODE_GPIO,</span><br><span> .gpio47 = GPIO_MODE_NATIVE,</span><br><span> .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_NATIVE,</span><br><span> .gpio50 = GPIO_MODE_GPIO,</span><br><span> .gpio51 = GPIO_MODE_GPIO,</span><br><span> .gpio52 = GPIO_MODE_GPIO,</span><br><span>@@ -146,15 +139,11 @@</span><br><span> static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span> .gpio33 = GPIO_DIR_OUTPUT,</span><br><span> .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio35 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio36 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio37 = GPIO_DIR_OUTPUT,</span><br><span> .gpio38 = GPIO_DIR_INPUT,</span><br><span> .gpio39 = GPIO_DIR_INPUT,</span><br><span> .gpio44 = GPIO_DIR_INPUT,</span><br><span> .gpio46 = GPIO_DIR_OUTPUT,</span><br><span> .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio49 = GPIO_DIR_OUTPUT,</span><br><span> .gpio50 = GPIO_DIR_INPUT,</span><br><span> .gpio51 = GPIO_DIR_INPUT,</span><br><span> .gpio52 = GPIO_DIR_INPUT,</span><br><span>@@ -168,11 +157,7 @@</span><br><span> </span><br><span> static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span> .gpio33 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio35 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio36 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio37 = GPIO_LEVEL_LOW,</span><br><span> .gpio46 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(0, 100%, 40%);">- .gpio49 = GPIO_LEVEL_LOW,</span><br><span> .gpio53 = GPIO_LEVEL_HIGH,</span><br><span> .gpio57 = GPIO_LEVEL_HIGH,</span><br><span> .gpio60 = GPIO_LEVEL_HIGH,</span><br><span>diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c</span><br><span>index 0d7389a..51869cb 100644</span><br><span>--- a/src/mainboard/hp/8770w/hda_verb.c</span><br><span>+++ b/src/mainboard/hp/8770w/hda_verb.c</span><br><span>@@ -4,6 +4,7 @@</span><br><span> * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span> * Copyright (C) 2014 Vladimir Serbinenko</span><br><span> * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or</span><br><span> * modify it under the terms of the GNU General Public License as</span><br><span>@@ -19,11 +20,11 @@</span><br><span> </span><br><span> const u32 cim_verb_data[] = {</span><br><span> 0x111d7605, /* Codec Vendor / Device ID: IDT */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x103c17c2, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x103c176c, /* Subsystem ID */</span><br><span> </span><br><span> 0x0000000b, /* Number of 4 dword sets */</span><br><span> /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(0, 100%, 40%);">- AZALIA_SUBVENDOR(0x0, 0x103c17c2),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x103c176c),</span><br><span> </span><br><span> /* NID 0x0a. */</span><br><span> AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030),</span><br><span>@@ -54,21 +55,6 @@</span><br><span> </span><br><span> /* NID 0x20. */</span><br><span> AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x80862806, /* Codec Vendor / Device ID: Intel */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x80860101, /* Subsystem ID */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00000004, /* Number of 4 dword sets */</span><br><span style="color: hsl(0, 100%, 40%);">- /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(0, 100%, 40%);">- AZALIA_SUBVENDOR(0x3, 0x80860101),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* NID 0x05. */</span><br><span style="color: hsl(0, 100%, 40%);">- AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* NID 0x06. */</span><br><span style="color: hsl(0, 100%, 40%);">- AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* NID 0x07. */</span><br><span style="color: hsl(0, 100%, 40%);">- AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),</span><br><span> };</span><br><span> </span><br><span> const u32 pc_beep_verbs[0] = {};</span><br><span>diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c</span><br><span>index b5fdecc..9e2634f 100644</span><br><span>--- a/src/mainboard/hp/8770w/mainboard.c</span><br><span>+++ b/src/mainboard/hp/8770w/mainboard.c</span><br><span>@@ -2,6 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or</span><br><span> * modify it under the terms of the GNU General Public License as</span><br><span>@@ -14,13 +15,10 @@</span><br><span> */</span><br><span> </span><br><span> #include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <drivers/intel/gma/int15.h></span><br><span> </span><br><span> static void mainboard_enable(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- GMA_INT15_PANEL_FIT_DEFAULT,</span><br><span style="color: hsl(0, 100%, 40%);">- GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> }</span><br><span> </span><br><span> struct chip_operations mainboard_ops = {</span><br><span>diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c</span><br><span>index bb9298c..f00c6f2 100644</span><br><span>--- a/src/mainboard/hp/8770w/romstage.c</span><br><span>+++ b/src/mainboard/hp/8770w/romstage.c</span><br><span>@@ -2,6 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -37,8 +38,9 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;</span><br><span> }</span><br><span> </span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span>@@ -76,5 +78,7 @@</span><br><span> void mainboard_get_spd(spd_raw_data *spd, bool id_only)</span><br><span> {</span><br><span> read_spd(&spd[0], 0x50, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[1], 0x51, id_only);</span><br><span> read_spd(&spd[2], 0x52, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[3], 0x53, id_only);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23628">change 23628</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23628"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I70477cfa314ed607b41b9096bc1b8664eff6baf0 </div>
<div style="display:none"> Gerrit-Change-Number: 23628 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Robert Reeves <xiinc37@gmail.com> </div>