<p>Vadim Bendebury has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23601">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: sort CPU_SPECIFIC_OPTIONS and drop duplicate<br><br>ACPI_NHLT happens to be selected twice.<br><br>BRANCH=none<br>BUG=none<br>TEST=generated fizz .config does not change<br><br>Change-Id: Ic525ee07015deb88fff4c15cad9dbbeada8a4479<br>Signed-off-by: Vadim Bendebury <vbendeb@chromium.org><br>---<br>M src/soc/intel/skylake/Kconfig<br>1 file changed, 11 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/23601/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index a486bd6..34893dc 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -15,33 +15,34 @@</span><br><span> config CPU_SPECIFIC_OPTIONS</span><br><span>         def_bool y</span><br><span>   select ACPI_INTEL_HARDWARE_SLEEP_VALUES</span><br><span style="color: hsl(120, 100%, 40%);">+       select ACPI_NHLT</span><br><span>     select ARCH_BOOTBLOCK_X86_32</span><br><span>         select ARCH_RAMSTAGE_X86_32</span><br><span>  select ARCH_ROMSTAGE_X86_32</span><br><span>  select ARCH_VERSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">-     select ACPI_NHLT</span><br><span>     select BOOTBLOCK_CONSOLE</span><br><span>     select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH</span><br><span>        select BOOT_DEVICE_SUPPORTS_WRITES</span><br><span>   select CACHE_MRC_SETTINGS</span><br><span>    select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE</span><br><span style="color: hsl(0, 100%, 40%);">-   select C_ENVIRONMENT_BOOTBLOCK</span><br><span>       select COLLECT_TIMESTAMPS</span><br><span>    select COMMON_FADT</span><br><span>   select CPU_INTEL_FIRMWARE_INTERFACE_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+     select C_ENVIRONMENT_BOOTBLOCK</span><br><span>       select GENERIC_GPIO_LIB</span><br><span style="color: hsl(120, 100%, 40%);">+       select HAVE_FSP_GOP</span><br><span>  select HAVE_HARD_RESET</span><br><span>       select HAVE_INTEL_FIRMWARE</span><br><span>   select HAVE_MONOTONIC_TIMER</span><br><span>  select HAVE_SMI_HANDLER</span><br><span>      select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">-   select NO_FIXED_XIP_ROM_SIZE</span><br><span>         select MRC_SETTINGS_PROTECT</span><br><span style="color: hsl(120, 100%, 40%);">+   select NO_FIXED_XIP_ROM_SIZE</span><br><span>         select PARALLEL_MP</span><br><span>   select PARALLEL_MP_AP_WORK</span><br><span>   select PCIEXP_ASPM</span><br><span style="color: hsl(0, 100%, 40%);">-      select PCIEXP_COMMON_CLOCK</span><br><span>   select PCIEXP_CLK_PM</span><br><span style="color: hsl(120, 100%, 40%);">+  select PCIEXP_COMMON_CLOCK</span><br><span>   select PCIEXP_L1_SUB_STATE</span><br><span>   select PCIEX_LENGTH_64MB</span><br><span>     select REG_SCRIPT</span><br><span>@@ -49,6 +50,8 @@</span><br><span>        select RELOCATABLE_RAMSTAGE</span><br><span>  select RTC</span><br><span>   select SA_ENABLE_DPR</span><br><span style="color: hsl(120, 100%, 40%);">+  select SMM_TSEG</span><br><span style="color: hsl(120, 100%, 40%);">+       select SMP</span><br><span>   select SOC_INTEL_COMMON</span><br><span>      select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span>     select SOC_INTEL_COMMON_BLOCK</span><br><span>@@ -59,17 +62,17 @@</span><br><span>  select SOC_INTEL_COMMON_BLOCK_EBDA</span><br><span>   select SOC_INTEL_COMMON_BLOCK_FAST_SPI</span><br><span>       select SOC_INTEL_COMMON_BLOCK_GPIO</span><br><span style="color: hsl(0, 100%, 40%);">-      select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL</span><br><span>     select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS</span><br><span style="color: hsl(120, 100%, 40%);">+      select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL</span><br><span>     select SOC_INTEL_COMMON_BLOCK_GRAPHICS</span><br><span>       select SOC_INTEL_COMMON_BLOCK_GSPI</span><br><span style="color: hsl(0, 100%, 40%);">-      select SOC_INTEL_COMMON_BLOCK_ITSS</span><br><span>   select SOC_INTEL_COMMON_BLOCK_I2C</span><br><span style="color: hsl(120, 100%, 40%);">+     select SOC_INTEL_COMMON_BLOCK_ITSS</span><br><span>   select SOC_INTEL_COMMON_BLOCK_LPC</span><br><span>    select SOC_INTEL_COMMON_BLOCK_LPSS</span><br><span>   select SOC_INTEL_COMMON_BLOCK_PCIE</span><br><span style="color: hsl(0, 100%, 40%);">-      select SOC_INTEL_COMMON_BLOCK_PMC</span><br><span>    select SOC_INTEL_COMMON_BLOCK_PCR</span><br><span style="color: hsl(120, 100%, 40%);">+     select SOC_INTEL_COMMON_BLOCK_PMC</span><br><span>    select SOC_INTEL_COMMON_BLOCK_RTC</span><br><span>    select SOC_INTEL_COMMON_BLOCK_SA</span><br><span>     select SOC_INTEL_COMMON_BLOCK_SATA</span><br><span>@@ -82,19 +85,15 @@</span><br><span>     select SOC_INTEL_COMMON_BLOCK_TIMER</span><br><span>  select SOC_INTEL_COMMON_BLOCK_UART</span><br><span>   select SOC_INTEL_COMMON_BLOCK_XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+    select SOC_INTEL_COMMON_GFX_OPREGION</span><br><span>         select SOC_INTEL_COMMON_NHLT</span><br><span>         select SOC_INTEL_COMMON_RESET</span><br><span style="color: hsl(0, 100%, 40%);">-   select SMM_TSEG</span><br><span style="color: hsl(0, 100%, 40%);">- select SMP</span><br><span>   select SSE2</span><br><span>  select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span>     select TSC_CONSTANT_RATE</span><br><span>     select TSC_MONOTONIC_TIMER</span><br><span>   select TSC_SYNC_MFENCE</span><br><span>       select UDELAY_TSC</span><br><span style="color: hsl(0, 100%, 40%);">-       select ACPI_NHLT</span><br><span style="color: hsl(0, 100%, 40%);">-        select HAVE_FSP_GOP</span><br><span style="color: hsl(0, 100%, 40%);">-     select SOC_INTEL_COMMON_GFX_OPREGION</span><br><span> </span><br><span> config MAINBOARD_USES_FSP2_0</span><br><span>     bool</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23601">change 23601</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23601"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic525ee07015deb88fff4c15cad9dbbeada8a4479 </div>
<div style="display:none"> Gerrit-Change-Number: 23601 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vadim Bendebury <vbendeb@chromium.org> </div>