<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23589">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Add SoC overrides for SATA initialization<br><br>SATA PCH configuration space registers bit mapping is different<br>for various SOCs hence common API between SPT-PCH and CNL-PCH causing<br>issue.<br><br>Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>A src/soc/intel/common/block/include/intelblocks/sata.h<br>M src/soc/intel/common/block/sata/sata.c<br>2 files changed, 27 insertions(+), 37 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/23589/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/include/intelblocks/sata.h b/src/soc/intel/common/block/include/intelblocks/sata.h</span><br><span>new file mode 100644</span><br><span>index 0000000..c726cea</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/sata.h</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_INTEL_COMMON_BLOCK_SATA_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_INTEL_COMMON_BLOCK_SATA_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SoC override SATA final initialization */</span><br><span style="color: hsl(120, 100%, 40%);">+void sata_soc_final(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_INTEL_COMMON_BLOCK_SATA_H */</span><br><span>diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c</span><br><span>index 791510e..f6a0a44 100644</span><br><span>--- a/src/soc/intel/common/block/sata/sata.c</span><br><span>+++ b/src/soc/intel/common/block/sata/sata.c</span><br><span>@@ -17,52 +17,20 @@</span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/sata.h></span><br><span> #include <soc/pci_devs.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SATA_ABAR_PORT_IMPLEMENTED 0x0c</span><br><span style="color: hsl(0, 100%, 40%);">-#define SATA_PCI_CFG_PORT_CTL_STS 0x92</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void *get_ahci_bar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+/* SoC override SATA final initialization */</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) void sata_soc_final(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t bar;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_SATA;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);</span><br><span style="color: hsl(0, 100%, 40%);">- return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * SATA Port control and Status. By default, the SATA ports are set (by HW)</span><br><span style="color: hsl(0, 100%, 40%);">- * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial</span><br><span style="color: hsl(0, 100%, 40%);">- * power on reset. When enabled by software as per SATA port mapping,</span><br><span style="color: hsl(0, 100%, 40%);">- * the ports can transition between the on, partial and slumber states</span><br><span style="color: hsl(0, 100%, 40%);">- * and can detect devices. When disabled, the port is in the off state and</span><br><span style="color: hsl(0, 100%, 40%);">- * can't detect any devices.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_final(device_t dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- void *ahcibar = get_ahci_bar();</span><br><span style="color: hsl(0, 100%, 40%);">- u32 port_impl, temp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = PCH_DEV_SATA;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Bus Master */</span><br><span style="color: hsl(0, 100%, 40%);">- temp = pci_read_config32(dev, PCI_COMMAND);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Read Ports Implemented (GHC_PI) */</span><br><span style="color: hsl(0, 100%, 40%);">- port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Port enable */</span><br><span style="color: hsl(0, 100%, 40%);">- temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- temp |= port_impl;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* no-op */</span><br><span> }</span><br><span> </span><br><span> static struct device_operations sata_ops = {</span><br><span> .read_resources = &pci_dev_read_resources,</span><br><span> .set_resources = &pci_dev_set_resources,</span><br><span> .enable_resources = &pci_dev_enable_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .final = sata_final,</span><br><span style="color: hsl(120, 100%, 40%);">+ .final = &sata_soc_final,</span><br><span> .ops_pci = &pci_dev_ops_pci,</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23589">change 23589</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a </div>
<div style="display:none"> Gerrit-Change-Number: 23589 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>