<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23592">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/sandybridge: Put stage cache into TSEG<br><br>TSEG is not accessible in ring 0 after it is locked in<br>ramstage, in contrast with cbmem which remains accessible. Assuming<br>SMM does not touch the cache this is a good region to cache stages.<br><br>TESTED on Thinkpad X220: on a cold boot the stage cache gets created<br>and on S3 the cached ramstage gets properly used.<br><br>Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_206ax/Kconfig<br>M src/cpu/intel/model_206ax/Makefile.inc<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>M src/northbridge/intel/sandybridge/sandybridge.h<br>5 files changed, 38 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/23592/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig</span><br><span>index f16b119..09311d1 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Kconfig</span><br><span>+++ b/src/cpu/intel/model_206ax/Kconfig</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #select AP_IN_SIPI_WAIT</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select CPU_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span> </span><br><span> config BOOTBLOCK_CPU_INIT</span><br><span> string</span><br><span>@@ -35,4 +36,12 @@</span><br><span> hex</span><br><span> default 0x800000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SMM_RESERVED_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config IED_REGION_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x400000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>index 7516e9d..1e04554 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>@@ -11,6 +11,9 @@</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 594dde1..9a50e2b 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -92,6 +92,26 @@</span><br><span> #define PSS_LATENCY_TRANSITION 10</span><br><span> #define PSS_LATENCY_BUSMASTER 10</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Region of SMM space is reserved for multipurpose use. It falls below</span><br><span style="color: hsl(120, 100%, 40%);">+ * the IED region and above the SMM handler. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define RESERVED_SMM_OFFSET \</span><br><span style="color: hsl(120, 100%, 40%);">+ (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Sanity check config options. */</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_SMM_TSEG_SIZE < 0x800000)</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_IED_REGION_SIZE is not a power of 2"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #ifdef __SMM__</span><br><span> /* Lock MSRs */</span><br><span> void intel_model_206ax_finalize_smm(void);</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>index da43de0..e80fa31 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>@@ -132,6 +132,10 @@</span><br><span> params->ied_base = tsegmb + params->smram_size;</span><br><span> params->ied_size = tseg_size - params->smram_size;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Adjust available SMM handler memory size. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))</span><br><span style="color: hsl(120, 100%, 40%);">+ params->smram_size -= CONFIG_SMM_RESERVED_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* SMRR has 32-bits of valid address aligned to 4KiB. */</span><br><span> params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;</span><br><span> params->smrr_base.hi = 0;</span><br><span>diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>index 1f56585..d446049 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>@@ -40,7 +40,8 @@</span><br><span> #define IVB_STEP_D0 (BASE_REV_IVB + 6)</span><br><span> </span><br><span> /* Intel Enhanced Debug region must be 4MB */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IED_SIZE 0x400000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IED_SIZE CONFIG_IED_REGION_SIZE</span><br><span> </span><br><span> /* Northbridge BARs */</span><br><span> #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23592">change 23592</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 </div>
<div style="display:none"> Gerrit-Change-Number: 23592 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>