<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23587">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] sb/intel/bd82x6x: Let mainboard override SPI opmenu<br><br>Change-Id: I9ceaf5b2d11365e21a2bebc9c5def1fcf0be8aad<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/southbridge/intel/bd82x6x/chip.h<br>M src/southbridge/intel/bd82x6x/finalize.c<br>M src/southbridge/intel/bd82x6x/lpc.c<br>3 files changed, 38 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/23587/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h</span><br><span>index e1064a7..042c286 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/chip.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/chip.h</span><br><span>@@ -95,6 +95,14 @@</span><br><span> </span><br><span> uint32_t spi_uvscc;</span><br><span> uint32_t spi_lvscc;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t opprefixes[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t is_write;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t needs_address;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t op;</span><br><span style="color: hsl(120, 100%, 40%);">+ } ops[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ } spi;</span><br><span> };</span><br><span> </span><br><span> #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>index fe28af0..9ccce84 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/finalize.c</span><br><span>@@ -17,8 +17,9 @@</span><br><span> #include <arch/io.h></span><br><span> #include <console/post_codes.h></span><br><span> #include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "pch.h"</span><br><span> #include <spi-generic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span> </span><br><span> void intel_pch_finalize_smm(void)</span><br><span> {</span><br><span>@@ -37,12 +38,6 @@</span><br><span> RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Set SPI opcode menu */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(0x3894) = SPI_OPPREFIX;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA16(0x3896) = SPI_OPTYPE;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x3898) = SPI_OPMENU_LOWER;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x389c) = SPI_OPMENU_UPPER;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Lock SPIBAR */</span><br><span> RCBA32_OR(0x3804, (1 << 15));</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>index 7f61669..42f51b5 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>@@ -827,6 +827,34 @@</span><br><span> </span><br><span> static void lpc_final(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 spi_opprefix = SPI_OPPREFIX;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 spi_optype = SPI_OPTYPE;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 spi_opmenu[2] = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure SPI opcode menu; devicetree may override defaults. */</span><br><span style="color: hsl(120, 100%, 40%);">+ const config_t *const config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config && config->spi.ops[0].op) {</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_opprefix = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_optype = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_opmenu[0] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_opmenu[1] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < sizeof(spi_opprefix); ++i)</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_opprefix |= config->spi.opprefixes[i] << i * 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < sizeof(spi_opmenu); ++i) {</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_optype |=</span><br><span style="color: hsl(120, 100%, 40%);">+ config->spi.ops[i].is_write << 2 * i |</span><br><span style="color: hsl(120, 100%, 40%);">+ config->spi.ops[i].needs_address << (2 * i + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_opmenu[i / 4] |=</span><br><span style="color: hsl(120, 100%, 40%);">+ config->spi.ops[i].op << (i % 4) * 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(0x3894) = spi_opprefix;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA16(0x3896) = spi_optype;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x3898) = spi_opmenu[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x389c) = spi_opmenu[1];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Call SMM finalize() handlers before resume */</span><br><span> if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {</span><br><span> if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23587">change 23587</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9ceaf5b2d11365e21a2bebc9c5def1fcf0be8aad </div>
<div style="display:none"> Gerrit-Change-Number: 23587 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>