<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23581">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/meowth: Limit Package PL2 to 11.625W<br><br>Meowth system's CPU heat sink have a designed limitation of 11.7W, hence<br>limit package PL2 (short turbo limit) to 11.625W( 93 * 125 MilliWatts).<br><br>BUG=b.72574971<br>TEST=Flash and boot up with meowth platform, check value with debug<br>build FSP.<br><br>Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/google/zoombini/variants/meowth/devicetree.cb<br>1 file changed, 5 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/23581/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>index 88de878..ef434cb 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>@@ -32,6 +32,11 @@</span><br><span>   register "ScsEmmcHs400Enabled" = "1"</span><br><span>     register "ScsSdCardEnabled" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+     # CPU Basic Management #</span><br><span style="color: hsl(120, 100%, 40%);">+      register "PPL1Power" = "0x38"       # 7W</span><br><span style="color: hsl(120, 100%, 40%);">+  register "PPL2_enable" = "1"        # Package PL2 enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PPL2Power" = "0x5D"       # 11.625W for Package PL2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>  # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM</span><br><span>     # communication before memory is up.</span><br><span>         register "gspi[0]" = "{</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23581">change 23581</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23581"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3aa16ba17f38f71bc5cb2e4cc7a226931e1503b2 </div>
<div style="display:none"> Gerrit-Change-Number: 23581 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>