<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23571">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/lars,lili: Update GPIO mapping<br><br>Combination of several commits from Chromium tree:<br>949037c [Lars: Coreboot GPIO changes for EVT]<br>c286789 [Lars: Set USB Type A current limit to 2A]<br>0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low]<br>4a0650d [Lili: Support touchscreen]<br><br>Disable unused GPIOs based on schematic and<br>adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK.<br><br>Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A<br>charging from the USB Type-A port.<br><br>GPP_F_23 is set to NC currently and is floating, causing the on-board<br>speaker to have no audio or the audio has noise; set to output/low.<br><br>These commits bring lars' GPIO mapping in line with the Chromium tree.<br><br>Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6<br>Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397<br>Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec<br>Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269<br>Original-Signed-off-by: David Wu <David_Wu@quantatw.com><br>Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com><br>Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com><br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br>Original-Tested-by: David Wu <david_wu@quantatw.com><br>Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com><br>Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com><br><br>Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/lars/gpio.h<br>1 file changed, 62 insertions(+), 62 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/23571/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h</span><br><span>index 77151a4..a05c702 100644</span><br><span>--- a/src/mainboard/google/lars/gpio.h</span><br><span>+++ b/src/mainboard/google/lars/gpio.h</span><br><span>@@ -63,14 +63,14 @@</span><br><span> /* LPC_LAD_3 */          PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),</span><br><span> /* LPC_FRAME */               PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),</span><br><span> /* LPC_SERIRQ */        PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PIRQA# */                /* GPP_A7 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PIRQA# */              PAD_CFG_NC(GPP_A7),</span><br><span> /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),</span><br><span> /* EC_LPC_CLK */        PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PCH_LPC_CLK */   /* GPP_A10 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EC_HID_INT */   /* GPP_A11 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_KB_PROX_INT */      PAD_CFG_GPO(GPP_A12, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_LPC_CLK */       PAD_CFG_NC(GPP_A10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_HID_INT */  PAD_CFG_NC(GPP_A11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_KB_PROX_INT */     PAD_CFG_NC(GPP_A12),</span><br><span> /* PCH_SUSPWRACB */     PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PM_SUS_STAT */  PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SUS_STAT */        PAD_CFG_NC(GPP_A14),</span><br><span> /* PCH_SUSACK */        PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span> /* SD_1P8_SEL */       PAD_CFG_NC(GPP_A16),</span><br><span> /* SD_PWR_EN */         PAD_CFG_NC(GPP_A17),</span><br><span>@@ -87,35 +87,35 @@</span><br><span> /* BT_RF_KILL */  PAD_CFG_NC(GPP_B4),</span><br><span> /* SRCCLKREQ0# */        PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */</span><br><span> /* WIFI_CLK_REQ */        PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ3# */   /* GPP_B8 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SSD_CLK_REQ */   PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ5# */   /* GPP_B10 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* MPHY_EXT_PWR_GATE */    PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* KEPLR_CLK_REQ */      PAD_CFG_NC(GPP_B7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_INT_WAK */        PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_CLK_REQ */       PAD_CFG_NC(GPP_B9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */  PAD_CFG_NC(GPP_B10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),</span><br><span> /* PM_SLP_S0 */           PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span> /* PCH_PLT_RST */      PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPP_B_14_SPKR */        PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */            /* GPP_B15 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_BUZZER */ PAD_CFG_GPO(GPP_B14, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */         PAD_CFG_NC(GPP_B15),</span><br><span> /* WLAN_PCIE_WAKE */    PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SSD_PCIE_WAKE */      PAD_CFG_GPI_GPIO_DRIVER(GPP_B17, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */   /* GPP_B18 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CCODEC_SPI_CS */        PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CODEC_SPI_CLK */        PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CODEC_SPI_MISO */       PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CODEC_SPI_MOSI */       PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1ALERT# */            PAD_CFG_GPO(GPP_B23, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_PCIE_WAKE */     PAD_CFG_NC(GPP_B17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */  PAD_CFG_NC(GPP_B18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CCODEC_SPI_CS */       PAD_CFG_NC(GPP_B19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_CLK */       PAD_CFG_NC(GPP_B20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_MISO */      PAD_CFG_NC(GPP_B21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_MOSI */      PAD_CFG_NC(GPP_B22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1ALERT# */           PAD_CFG_NC(GPP_B23),</span><br><span> /* SMB_CLK */           PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span> /* SMB_DATA */          PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),</span><br><span> /* SMBALERT# */         PAD_CFG_GPO(GPP_C2, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* M2_WWAN_PWREN */        PAD_CFG_GPO(GPP_C3, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0DATA */             PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0ALERT# */    PAD_CFG_GPO(GPP_C5, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_WWAN_PWREN */      PAD_CFG_NC(GPP_C3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */             PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */   PAD_CFG_NC(GPP_C5),</span><br><span> /* EC_IN_RW */           PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB_CTL */               PAD_CFG_GPO(GPP_C7, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RXD */            /* GPP_C8 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_TXD */             /* GPP_C9 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* NFC_RST* */              PAD_CFG_GPO(GPP_C10, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EN_PP3300_KEPLER */    PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_CTL */              PAD_CFG_NC(GPP_C7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */            PAD_CFG_NC(GPP_C8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */            PAD_CFG_NC(GPP_C9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* NFC_RST* */             PAD_CFG_NC(GPP_C10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_KEPLER */    PAD_CFG_NC(GPP_C11),</span><br><span> /* PCH_MEM_CFG0 */      PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),</span><br><span> /* PCH_MEM_CFG1 */     PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),</span><br><span> /* PCH_MEM_CFG2 */     PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),</span><br><span>@@ -128,29 +128,29 @@</span><br><span> /* GD_UART2_TXD */     PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span> /* TCH_PNL_PWREN */    PAD_CFG_GPO(GPP_C22, 1, DEEP),</span><br><span> /* SPI_WP_STATUS */   PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ITCH_SPI_CS */        /* GPP_D0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ITCH_SPI_CLK */  /* GPP_D1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ITCH_SPI_MISO_1 */       /* GPP_D2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ITCH_SPI_MISO_0 */       /* GPP_D3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CAM_FLASH_STROBE */      PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EN_PP3300_DX_EMMC */     PAD_CFG_GPO(GPP_D5, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EN_PP1800_DX_EMMC */    PAD_CFG_GPO(GPP_D6, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SH_I2C1_SDA */  PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SH_I2C1_SCL */   PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-                    PAD_CFG_GPO(GPP_D9, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB_A0_ILIM_SEL */      PAD_CFG_GPO(GPP_D10, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB_A1_ILIM_SEL */     PAD_CFG_GPO(GPP_D11, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EN_PP3300_DX_CAM */    PAD_CFG_GPO(GPP_D12, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_CS */       PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_MISO_1 */      PAD_CFG_NC(GPP_D2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_MISO_0 */      PAD_CFG_NC(GPP_D3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CAM_FLASH_STROBE */     PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SH_I2C1_SDA */        PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SH_I2C1_SCL */  PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CSB */  PAD_CFG_NC(GPP_D9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_A0_ILIM_SEL */      PAD_CFG_GPO(GPP_D10, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_A1_ILIM_SEL */   PAD_CFG_GPO(GPP_D11, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_DX_CAM */  PAD_CFG_NC(GPP_D12),</span><br><span> /* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_TXD */       /* GPP_D14 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RTS */        /* GPP_D15 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_CTS */        /* GPP_D16 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */      PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS */       PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS */       PAD_CFG_NC(GPP_D16),</span><br><span> /* DMIC_CLK_1 */        PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span> /* DMIC_DATA_1 */      PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),</span><br><span> /* DMIC_CLK_0 */       PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span> /* DMIC_DATA_0 */      PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ITCH_SPI_D2 */  /* GPP_D21 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ITCH_SPI_D3 */  /* GPP_D22 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_D2 */        PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22),</span><br><span> /* I2S_MCLK */          PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span> /* SPI_TPM_IRQ */      PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),</span><br><span> /* SATAXPCIE1 */     PAD_CFG_NC(GPP_E1),</span><br><span>@@ -159,7 +159,7 @@</span><br><span> /* SSD_SATA_DEVSLP */      PAD_CFG_NC(GPP_E4),</span><br><span> /* SATA_DEVSLP1 */       PAD_CFG_NC(GPP_E5),</span><br><span> /* SATA_DEVSLP2 */       PAD_CFG_NC(GPP_E6),</span><br><span style="color: hsl(0, 100%, 40%);">-/* TCH_PNL_INTR* */  PAD_CFG_NC(GPP_E7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_PNL_INTR* */        PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),</span><br><span> /* SATALED# */               PAD_CFG_NC(GPP_E8),</span><br><span> /* USB2_OC_0 */          PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span> /* USB2_OC_1 */         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span>@@ -174,7 +174,7 @@</span><br><span> /* DDPB_CTRLDATA */      PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),</span><br><span> /* DDPC_CTRLCLK */     PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),</span><br><span> /* DDPC_CTRLDATA */    PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E22, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLCLK */       PAD_CFG_NC(GPP_E22),</span><br><span> /* TCH_PNL_RST */       PAD_CFG_GPO(GPP_E23, 1, DEEP),</span><br><span> /* I2S2_SCLK */               PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),</span><br><span> /* I2S2_SFRM */         PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),</span><br><span>@@ -182,8 +182,8 @@</span><br><span> /* I2S2_RXD */            PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),</span><br><span> /* I2C2_SDA */          PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),</span><br><span> /* I2C2_SCL */          PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SDA */              /* GPP_F6 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SCL */              /* GPP_F7 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */            PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */             PAD_CFG_NC(GPP_F7),</span><br><span> /* I2C4_SDA */           PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),</span><br><span> /* I2C4_SCL */              PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),</span><br><span> /* AUDIO_IRQ */             PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),</span><br><span>@@ -199,15 +199,15 @@</span><br><span> /* EMMC_DATA7 */    PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),</span><br><span> /* EMMC_RCLK */                PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),</span><br><span> /* EMMC_CLK */         PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-                   /* GPP_F23 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */               /* GPP_G0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA0 */              /* GPP_G1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA1 */              /* GPP_G2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA2 */              /* GPP_G3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA3 */              /* GPP_G4 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CD# */                /* GPP_G5 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CLK */                /* GPP_G6 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_WP */         /* GPP_G7 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* BOOT_BEEP */           PAD_CFG_GPO(GPP_F23, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */            PAD_CFG_NC(GPP_G0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */             PAD_CFG_NC(GPP_G1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */             PAD_CFG_NC(GPP_G2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */             PAD_CFG_NC(GPP_G3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */             PAD_CFG_NC(GPP_G4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */               PAD_CFG_NC(GPP_G5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */               PAD_CFG_NC(GPP_G6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */                PAD_CFG_NC(GPP_G7),</span><br><span> /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span> /* EC_PCH_ACPRESENT */    PAD_CFG_NF(GPD1, NONE, DEEP, NF1),</span><br><span> /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),</span><br><span>@@ -215,11 +215,11 @@</span><br><span> /* PM_SLP_S3# */  PAD_CFG_NF(GPD4, NONE, DEEP, NF1),</span><br><span> /* PM_SLP_S4# */  PAD_CFG_NF(GPD5, NONE, DEEP, NF1),</span><br><span> /* PM_SLP_SA# */  PAD_CFG_NF(GPD6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-                      /* GPD7 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPD7 */          PAD_CFG_NC(GPD7),</span><br><span> /* PM_SUSCLK */            PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* PCH_SLP_WLAN# */   /* GPD9 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PM_SLP_S5# */      PAD_CFG_NF(GPD10, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* LANPHYC */                /* GPD11 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SLP_WLAN# */        PAD_CFG_NC(GPD9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S5# */     PAD_CFG_NC(GPD10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */               PAD_CFG_NC(GPD11),</span><br><span> };</span><br><span> </span><br><span> /* Early pad configuration in romstage. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23571">change 23571</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23571"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf </div>
<div style="display:none"> Gerrit-Change-Number: 23571 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: David Wu <david_wu@quantatw.com> </div>