<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23547">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9<br><br>Update the shared AGESA headers to 1.3.0.9.<br><br>This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated<br>to the same version.<br><br>Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/vendorcode/amd/pi/00670F00/AGESA.h<br>M src/vendorcode/amd/pi/00670F00/AMD.h<br>M src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h<br>M src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h<br>M src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h<br>M src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h<br>9 files changed, 89 insertions(+), 77 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/23547/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h</span><br><span>index 09a1680..17f6986 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/AGESA.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/AGESA.h</span><br><span>@@ -13,7 +13,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -1800,6 +1800,14 @@</span><br><span> } DEVICE_BLOCK_HEADER;</span><br><span> </span><br><span> ///===============================================================================</span><br><span style="color: hsl(120, 100%, 40%);">+/// CPU_VREF_OVERRIDE</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct _CPU_VREF_OVERRIDE{</span><br><span style="color: hsl(120, 100%, 40%);">+ IN UINT8 VrefOp; ///< Operater to adjust VrefHspeed</span><br><span style="color: hsl(120, 100%, 40%);">+ IN UINT8 VrefOffset; ///< Offset to adjust VrefHspeed</span><br><span style="color: hsl(120, 100%, 40%);">+} CPU_VREF_OVERRIDE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+///===============================================================================</span><br><span> /// MEM_PARAMETER_STRUCT</span><br><span> /// This data structure is used to pass wrapper parameters to the memory configuration code</span><br><span> ///</span><br><span>@@ -2116,6 +2124,8 @@</span><br><span> ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE}</span><br><span> IN UINT16 CustomVddioSupport; ///< CustomVddioSupport</span><br><span> ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE}</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CPU_VREF_OVERRIDE CpuVrefOverride[2][4]; ///< Structure to adjust VrefHspeed</span><br><span style="color: hsl(120, 100%, 40%);">+ ///< PerDct, Per MemPstate</span><br><span> } MEM_PARAMETER_STRUCT;</span><br><span> </span><br><span> </span><br><span>@@ -2858,6 +2868,7 @@</span><br><span> IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control</span><br><span> IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround</span><br><span> IN BOOLEAN CfgFchUsbPortDisWorkAround; ///< FCH USB Workaround</span><br><span style="color: hsl(120, 100%, 40%);">+ IN BOOLEAN CfgFchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update</span><br><span> } FCH_PLATFORM_POLICY;</span><br><span> </span><br><span> </span><br><span>@@ -2993,7 +3004,7 @@</span><br><span> ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}</span><br><span> IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate</span><br><span> ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}</span><br><span style="color: hsl(0, 100%, 40%);">- IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy</span><br><span> </span><br><span> IN BOOLEAN CfgIommuSupport; ///< IOMMU support</span><br><span> IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing</span><br><span>@@ -3087,6 +3098,7 @@</span><br><span> IN BOOLEAN CfgAcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING}</span><br><span> IN BOOLEAN CfgSmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING}</span><br><span> IN BOOLEAN CfgSmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR}</span><br><span style="color: hsl(120, 100%, 40%);">+ IN UINT16 CfgBootUpDisplayDevice; ///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE}</span><br><span> IN BOOLEAN Reserved; ///< reserved...</span><br><span> } BUILD_OPT_CFG;</span><br><span> </span><br><span>@@ -3171,6 +3183,9 @@</span><br><span> IN BOOLEAN AcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING}</span><br><span> IN BOOLEAN SmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING}</span><br><span> IN BOOLEAN SmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR}</span><br><span style="color: hsl(120, 100%, 40%);">+ IN UINT16 BootUpDisplayDevice; ///< The boot up display device selected.</span><br><span style="color: hsl(120, 100%, 40%);">+ ///< If equal to 0 default setting in VBIOS for boot up display devices</span><br><span style="color: hsl(120, 100%, 40%);">+ ///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE}</span><br><span> } PLATFORM_CONFIGURATION;</span><br><span> </span><br><span> </span><br><span>@@ -3404,6 +3419,7 @@</span><br><span> OUT UINT8 Channel:2; ///< Channel ID</span><br><span> OUT UINT8 Dimm:2; ///< DIMM ID</span><br><span> OUT UINT8 DimmPresent:1; ///< Dimm Present</span><br><span style="color: hsl(120, 100%, 40%);">+ OUT BOOLEAN Interleaved; ///< Interleaved;</span><br><span> OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range</span><br><span> ///< of memory mapped to the referenced Memory Device.</span><br><span> OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/AMD.h b/src/vendorcode/amd/pi/00670F00/AMD.h</span><br><span>index c4d56c9..483ee32 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/AMD.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/AMD.h</span><br><span>@@ -13,7 +13,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -45,12 +45,8 @@</span><br><span> #ifndef _AMD_H_</span><br><span> #define _AMD_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define AGESA_REVISION "Arch2008"</span><br><span style="color: hsl(0, 100%, 40%);">-#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}</span><br><span style="color: hsl(120, 100%, 40%);">+#define AGESA_ID "AGESA"</span><br><span> </span><br><span> //</span><br><span> //</span><br><span>@@ -58,8 +54,11 @@</span><br><span> //</span><br><span> //</span><br><span> #define LAST_ENTRY 0xFFFFFFFFul</span><br><span style="color: hsl(120, 100%, 40%);">+#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)</span><br><span> #define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')</span><br><span style="color: hsl(120, 100%, 40%);">+/* coreboot binaryPI - start */</span><br><span> #define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')</span><br><span style="color: hsl(120, 100%, 40%);">+/* coreboot binaryPI - end */</span><br><span> #define IOCF8 0xCF8</span><br><span> #define IOCFC 0xCFC</span><br><span> </span><br><span>@@ -130,37 +129,27 @@</span><br><span> /// AGESA struct name</span><br><span> typedef enum {</span><br><span> // AGESA BASIC FUNCTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_INIT_RESET = 0x00040000,</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_INIT_ENV = 0x00041000,</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_INIT_MID = 0x00042000,</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_INIT_LATE = 0x00043000,</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_INIT_S3_EARLY_RESTORE = 0x00044000,</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_INIT_S3_LATE_RESTORE = 0x00045000,</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_SET_VALUE_invalid = 0x00081000,</span><br><span style="color: hsl(0, 100%, 40%);">- AMD_GET_VALUE_invalid = 0x00082000</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_CREATE_STRUCT, ///< AmdCreateStruct handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_EARLY, ///< AmdInitEarly entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_ENV, ///< AmdInitEnv entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_LATE, ///< AmdInitLate entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_MID, ///< AmdInitMid entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_POST, ///< AmdInitPost entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_RESET, ///< AmdInitReset entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_RESUME, ///< AmdInitResume entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle</span><br><span style="color: hsl(120, 100%, 40%);">+ AMD_INIT_RTB ///< AmdInitRtb entry point handle</span><br><span> } AGESA_STRUCT_NAME;</span><br><span> </span><br><span> /* ResetType constant values */</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h</span><br><span>index 75169cb..1d53990 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h</span><br><span>@@ -14,7 +14,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -656,7 +656,7 @@</span><br><span> */</span><br><span> typedef struct {</span><br><span> REGISTER_TABLE_TIME_POINT TimePoint; ///< Time point</span><br><span style="color: hsl(0, 100%, 40%);">- CONST REGISTER_TABLE** TableList; ///< The table list.</span><br><span style="color: hsl(120, 100%, 40%);">+ CONST REGISTER_TABLE* CONST * CONST TableList; ///< The table list.</span><br><span> } REGISTER_TABLE_AT_GIVEN_TP;</span><br><span> /*------------------------------------------------------------------------------------------*/</span><br><span> /*</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h</span><br><span>index f4ffd49..9331cd1 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuFamilyTranslation.h</span><br><span>@@ -13,7 +13,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -164,7 +164,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef AGESA_STATUS F_CPU_DISABLE_PSTATE (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN UINT8 StateNumber,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -185,7 +185,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN UINT8 StateNumber,</span><br><span> IN BOOLEAN WaitForChange,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span>@@ -210,7 +210,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef BOOLEAN F_CPU_GET_IDD_MAX (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN UINT8 StateNumber,</span><br><span> OUT UINT32 *ProcIddMax,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span>@@ -231,7 +231,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef AGESA_STATUS F_CPU_GET_TSC_RATE (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES * FamilySpecificServices,</span><br><span> OUT UINT32 *FreqInMHz,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -252,7 +252,7 @@</span><br><span> * @retval AGESA_SUCCESS FreqInMHz is valid.</span><br><span> */</span><br><span> typedef AGESA_STATUS F_CPU_GET_NB_FREQ (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> OUT UINT32 *FreqInMHz,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -276,7 +276,7 @@</span><br><span> * @retval AGESA_STATUS Northbridge frequency is valid</span><br><span> */</span><br><span> typedef AGESA_STATUS F_CPU_GET_MIN_MAX_NB_FREQ (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN PLATFORM_CONFIGURATION *PlatformConfig,</span><br><span> IN PCI_ADDR *PciAddress,</span><br><span> OUT UINT32 *MinFreqInMHz,</span><br><span>@@ -306,7 +306,7 @@</span><br><span> * @retval FALSE NbPstate is disabled or invalid</span><br><span> */</span><br><span> typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN PLATFORM_CONFIGURATION *PlatformConfig,</span><br><span> IN PCI_ADDR *PciAddress,</span><br><span> IN UINT32 NbPstate,</span><br><span>@@ -333,7 +333,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN PCI_ADDR *PciAddress,</span><br><span> OUT BOOLEAN *NbVidUpdateAll,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span>@@ -358,7 +358,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef BOOLEAN F_CPU_GET_NB_IDD_MAX (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN UINT8 StateNumber,</span><br><span> OUT UINT32 *NbIddMax,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span>@@ -381,7 +381,7 @@</span><br><span> * @retval FALSE The core was previously launched, or has a problem.</span><br><span> */</span><br><span> typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN UINT32 CoreNumber,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -401,7 +401,7 @@</span><br><span> * @return One-based number of physical cores on current processor</span><br><span> */</span><br><span> typedef UINT8 F_CPU_NUMBER_OF_PHYSICAL_CORES (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span> </span><br><span>@@ -420,7 +420,7 @@</span><br><span> * @return The AP's unique core number</span><br><span> */</span><br><span> typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span> </span><br><span>@@ -449,7 +449,7 @@</span><br><span> * @retval CoreIdPositionOne Core Id is low</span><br><span> */</span><br><span> typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span> </span><br><span>@@ -468,7 +468,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef VOID (F_CPU_SET_WARM_RESET_FLAG) (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader,</span><br><span> IN WARM_RESET_REQUEST *Request</span><br><span> );</span><br><span>@@ -488,7 +488,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef VOID (F_CPU_GET_WARM_RESET_FLAG) (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader,</span><br><span> OUT WARM_RESET_REQUEST *Request</span><br><span> );</span><br><span>@@ -509,7 +509,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> OUT CONST VOID **FamilySpecificArray,</span><br><span> OUT UINT8 *NumberOfElements,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span>@@ -530,7 +530,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN OUT PLATFORM_FEATS *FeaturesUnion,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -552,7 +552,7 @@</span><br><span> * @retval FALSE The NB PState feature is not enabled.</span><br><span> */</span><br><span> typedef BOOLEAN F_IS_NB_PSTATE_ENABLED (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> IN PLATFORM_CONFIGURATION *PlatformConfig,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -571,7 +571,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef REGISTER_TABLE_AT_GIVEN_TP *F_GET_REGISTER_TABLE_LIST (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span> /// Reference to a Method.</span><br><span>@@ -590,7 +590,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef F_FAM_SPECIFIC_WORKAROUND **F_GET_WORKAROUND_TABLE (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span> OUT UINT16 *NumberOfWorkaroundTableEntries,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -614,7 +614,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef VOID F_PERFORM_EARLY_INIT_ON_CORE (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span> IN AMD_CPU_EARLY_PARAMS *EarlyParams,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span> );</span><br><span>@@ -644,7 +644,7 @@</span><br><span> *</span><br><span> */</span><br><span> typedef VOID F_GET_EARLY_INIT_TABLE (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilyServices,</span><br><span> OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,</span><br><span> IN AMD_CPU_EARLY_PARAMS *EarlyParams,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span>@@ -853,7 +853,7 @@</span><br><span> */</span><br><span> VOID</span><br><span> GetEmptyArray (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_SPECIFIC_SERVICES *FamilySpecificServices,</span><br><span> OUT CONST VOID **Empty,</span><br><span> OUT UINT8 *NumberOfElements,</span><br><span> IN AMD_CONFIG_PARAMS *StdHeader</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h</span><br><span>index 4d10b42..46906a8 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h</span><br><span>@@ -14,7 +14,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -236,7 +236,7 @@</span><br><span> /// Logical CPU ID Table</span><br><span> typedef struct {</span><br><span> IN UINT32 Elements; ///< Number of Elements</span><br><span style="color: hsl(0, 100%, 40%);">- IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer</span><br><span style="color: hsl(120, 100%, 40%);">+ IN CONST CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer</span><br><span> } LOGICAL_ID_TABLE;</span><br><span> </span><br><span> // MSRs</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h</span><br><span>index 46e5b17..21f73a3 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h</span><br><span>@@ -14,7 +14,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -937,6 +937,7 @@</span><br><span> UINT32 FchCpuId; ///< Saving CpuId for FCH Module.</span><br><span> BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )</span><br><span> FCH_CS FchCsSupport; ///< FCH Cs function structure</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOLEAN FchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update</span><br><span> } FCH_MISC;</span><br><span> </span><br><span> </span><br><span>@@ -1405,7 +1406,7 @@</span><br><span> ///PTUSBTxStructure</span><br><span> typedef struct {</span><br><span> PT_USB31Tx USB31Tx[2]; ///< USB31Tx setting</span><br><span style="color: hsl(0, 100%, 40%);">-PT_USB30Tx USB30Tx[3]; ///< USB30Tx setting</span><br><span style="color: hsl(120, 100%, 40%);">+PT_USB30Tx USB30Tx[6]; ///< USB30Tx setting</span><br><span> UINT8 USB20B2Tx00; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[0]</span><br><span> UINT8 USB20B2Tx05; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[5]</span><br><span> UINT8 USB20B3Tx1113; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[13][11]</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h</span><br><span>index 45453a8..c80dc52 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h</span><br><span>@@ -14,7 +14,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -81,6 +81,7 @@</span><br><span> BOOLEAN FchCheckCZ (IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> BOOLEAN FchCheckPackageAM4 (IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> UINT64 FchGetScratchFuse (IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+VOID FchInitResetRequest (IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> </span><br><span> ///</span><br><span> /// Fch Ab Routines</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h</span><br><span>index 304ed23..04784fe 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h</span><br><span>@@ -14,7 +14,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -115,6 +115,6 @@</span><br><span> #include "FchBiosRamUsage.h"</span><br><span> #include "AmdFch.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-extern BUILD_OPT_CFG UserOptions;</span><br><span style="color: hsl(120, 100%, 40%);">+extern CONST BUILD_OPT_CFG UserOptions;</span><br><span> </span><br><span> #endif // _FCH_PLATFORM_H_</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h b/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h</span><br><span>index 016d822..5811eb0 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/OptionsIds.h</span><br><span>@@ -13,7 +13,7 @@</span><br><span> */</span><br><span> /*****************************************************************************</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.</span><br><span> * All rights reserved.</span><br><span> *</span><br><span> * Redistribution and use in source and binary forms, with or without</span><br><span>@@ -87,6 +87,8 @@</span><br><span> * IDSOPT_PERF_ANALYSIS</span><br><span> * IDSOPT_ASSERT_ENABLED</span><br><span> * IDS_DEBUG_PORT</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDS_DEBUG_PORT_SIZE_IN_BYTES</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDS_DEBUG_TP_PREFIX</span><br><span> * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED</span><br><span> * IDSOPT_DEBUG_CODE_ENABLED</span><br><span> * IDSOPT_IDT_EXCEPTION_TRAP</span><br><span>@@ -94,12 +96,10 @@</span><br><span> *</span><br><span> **/</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//#include "Ids.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define IDSOPT_ERROR_TRAP_ENABLED FALSE</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define IDS_MMAP_SERIAL_PORT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #ifdef DEBUG</span><br><span> #define IDSOPT_IDS_ENABLED TRUE</span><br><span> //#define IDSOPT_CONTROL_ENABLED FALSE</span><br><span>@@ -109,12 +109,17 @@</span><br><span> #undef IDS_DEBUG_PRINT_MASK</span><br><span> #endif</span><br><span> #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_ALL | GFX_MISC | CPU_TRACE_ALL | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef IDS_MMAP_SERIAL_PORT</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDSOPT_SERIAL_PORT 0xfedc6000</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> #define IDSOPT_SERIAL_PORT 0x3F8</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #define IDSOPT_HEAP_CHECKING TRUE</span><br><span> #define IDSOPT_TRACE_BLD_CFG TRUE</span><br><span> #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE</span><br><span> #define IDSOPT_DEBUG_CODE_ENABLED TRUE</span><br><span> #define IDSOPT_C_OPTIMIZATION_DISABLED TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDSOPT_ASSERT_ENABLED TRUE</span><br><span> #else</span><br><span> #define IDSOPT_IDS_ENABLED FALSE</span><br><span> //#define IDSOPT_ERROR_TRAP_ENABLED FALSE</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23547">change 23547</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23547"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f </div>
<div style="display:none"> Gerrit-Change-Number: 23547 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>