<p>Shelley Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23527">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Set PsysPl3 and Pl4<br><br>If given a value for PsysPl3 and/or Pl4, set the<br>appropriate MSR.<br><br>BUG=b:71594855<br>BRANCH=None<br>TEST=boot up and check MSRs in OS to make sure values are<br> set as expected.<br><br>Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed<br>Signed-off-by: Shelley Chen <shchen@chromium.org><br>---<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/cpu.c<br>M src/soc/intel/skylake/include/soc/msr.h<br>4 files changed, 39 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/23527/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index 45f201c..7aa81f0 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -114,6 +114,8 @@</span><br><span> #define PKG_POWER_LIMIT_CLAMP (1 << 16)</span><br><span> #define PKG_POWER_LIMIT_TIME_SHIFT 17</span><br><span> #define PKG_POWER_LIMIT_TIME_MASK (0x7f)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f)</span><br><span> /* SMM save state MSRs */</span><br><span> #define SMBASE_MSR 0xc20</span><br><span> #define IEDBASE_MSR 0xc22</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 4e8cb81..6568701 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -100,6 +100,12 @@</span><br><span> /* SysPL2 Value in Watts */</span><br><span> u32 tdp_psyspl2;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* SysPL3 Value in Watts */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tdp_psyspl3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PL4 Value in Watts */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tdp_pl4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * The following fields come from FspUpdVpd.h.</span><br><span> * These are configuration values that are passed to FSP during</span><br><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 291a40d..f3da826 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -191,6 +191,36 @@</span><br><span> wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set PsysPl3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (conf->tdp_psyspl3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ limit = rdmsr(MSR_PL3_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ limit.lo = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ conf->tdp_psyspl3);</span><br><span style="color: hsl(120, 100%, 40%);">+ limit.lo |= (conf->tdp_psyspl3 * power_unit) &</span><br><span style="color: hsl(120, 100%, 40%);">+ PKG_POWER_LIMIT_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PsysPl3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ limit.lo |= PKG_POWER_LIMIT_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set max possible time window */</span><br><span style="color: hsl(120, 100%, 40%);">+ limit.lo |= PKG_POWER_LIMIT_TIME_MASK <<</span><br><span style="color: hsl(120, 100%, 40%);">+ PKG_POWER_LIMIT_TIME_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set minimum duty cycle */</span><br><span style="color: hsl(120, 100%, 40%);">+ limit.lo |= PKG_POWER_LIMIT_DUTYCYCLE_MASK <<</span><br><span style="color: hsl(120, 100%, 40%);">+ PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PL3_CONTROL, limit);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Pl4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (conf->tdp_pl4) {</span><br><span style="color: hsl(120, 100%, 40%);">+ limit = rdmsr(MSR_VR_CURRENT_CONFIG);</span><br><span style="color: hsl(120, 100%, 40%);">+ limit.lo = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU PsysPL4 = %u Watts\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ conf->tdp_pl4);</span><br><span style="color: hsl(120, 100%, 40%);">+ limit.lo |= (conf->tdp_pl4 * power_unit) &</span><br><span style="color: hsl(120, 100%, 40%);">+ PKG_POWER_LIMIT_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_VR_CURRENT_CONFIG, limit);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Set DDR RAPL power limit by copying from MMIO to MSR */</span><br><span> msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);</span><br><span> msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>index 0bd7f3c..780f94f 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5</span><br><span> #define MSR_VR_CURRENT_CONFIG 0x601</span><br><span> #define MSR_VR_MISC_CONFIG 0x603</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PL3_CONTROL 0x615</span><br><span> #define MSR_VR_MISC_CONFIG2 0x636</span><br><span> #define MSR_PP0_POWER_LIMIT 0x638</span><br><span> #define MSR_PP1_POWER_LIMIT 0x640</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23527">change 23527</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23527"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed </div>
<div style="display:none"> Gerrit-Change-Number: 23527 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>