<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23510">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Always add PM1_TMR block to FADT<br><br>Provide the PM1_TMR information in the FADT even if PmTimerDisabled is<br>set because PM timer emulation is enabled via MSR 121h so the timer will<br>still work and can be used by things like Tianocore and Windows.<br><br>Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/skylake/acpi.c<br>1 file changed, 8 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23510/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c</span><br><span>index 61360da..0839927 100644</span><br><span>--- a/src/soc/intel/skylake/acpi.c</span><br><span>+++ b/src/soc/intel/skylake/acpi.c</span><br><span>@@ -247,16 +247,14 @@</span><br><span>       fadt->pm1a_cnt_blk = pmbase + PM1_CNT;</span><br><span>    fadt->pm1b_cnt_blk = 0x0;</span><br><span>         fadt->pm2_cnt_blk = pmbase + PM2_CNT;</span><br><span style="color: hsl(0, 100%, 40%);">-        if (config->PmTimerDisabled == 0)</span><br><span style="color: hsl(0, 100%, 40%);">-            fadt->pm_tmr_blk = pmbase + PM1_TMR;</span><br><span style="color: hsl(120, 100%, 40%);">+       fadt->pm_tmr_blk = pmbase + PM1_TMR;</span><br><span>      fadt->gpe0_blk = pmbase + GPE0_STS(0);</span><br><span>    fadt->gpe1_blk = 0;</span><br><span> </span><br><span>   fadt->pm1_evt_len = 4;</span><br><span>    fadt->pm1_cnt_len = 2;</span><br><span>    fadt->pm2_cnt_len = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-       if (config->PmTimerDisabled == 0)</span><br><span style="color: hsl(0, 100%, 40%);">-            fadt->pm_tmr_len = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+      fadt->pm_tmr_len = 4;</span><br><span>     /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */</span><br><span>       fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);</span><br><span>         fadt->gpe1_blk_len = 0;</span><br><span>@@ -323,14 +321,12 @@</span><br><span>   fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;</span><br><span>     fadt->x_pm2_cnt_blk.addrh = 0x0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (config->PmTimerDisabled == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">-          fadt->x_pm_tmr_blk.space_id = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-             fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;</span><br><span style="color: hsl(0, 100%, 40%);">-              fadt->x_pm_tmr_blk.bit_offset = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-           fadt->x_pm_tmr_blk.resv = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;</span><br><span style="color: hsl(0, 100%, 40%);">-         fadt->x_pm_tmr_blk.addrh = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">-      }</span><br><span style="color: hsl(120, 100%, 40%);">+     fadt->x_pm_tmr_blk.space_id = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+   fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;</span><br><span style="color: hsl(120, 100%, 40%);">+    fadt->x_pm_tmr_blk.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_pm_tmr_blk.resv = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+       fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;</span><br><span style="color: hsl(120, 100%, 40%);">+       fadt->x_pm_tmr_blk.addrh = 0x0;</span><br><span> </span><br><span>       fadt->x_gpe0_blk.space_id = 0;</span><br><span>    fadt->x_gpe0_blk.bit_width = 0;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23510">change 23510</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23510"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8 </div>
<div style="display:none"> Gerrit-Change-Number: 23510 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>