<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23511">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Add devicetree variable for PCIe HotPlug<br><br>Add a variable to fill out the FSP UPD variable for PCIe HotPlug,<br>which allows a mainboard to enable HotPlug on individual root ports.<br><br>BUG=b:72417777<br>TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux<br>that it is identified as a HotPlug capable root port.<br><br>Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>3 files changed, 7 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/23511/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c</span><br><span>index 8002270..f60c08d 100644</span><br><span>--- a/src/soc/intel/skylake/chip.c</span><br><span>+++ b/src/soc/intel/skylake/chip.c</span><br><span>@@ -121,6 +121,8 @@</span><br><span>                   sizeof(params->PcieRpClkReqSupport));</span><br><span>     memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,</span><br><span>                         sizeof(params->PcieRpClkReqNumber));</span><br><span style="color: hsl(120, 100%, 40%);">+       memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,</span><br><span style="color: hsl(120, 100%, 40%);">+                    sizeof(params->PcieRpHotPlug));</span><br><span> </span><br><span>       params->EnableLan = config->EnableLan;</span><br><span>         params->Cio2Enable = config->Cio2Enable;</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 4e8cb81..b019631 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -218,6 +218,9 @@</span><br><span>     */</span><br><span>  u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+        /* Enable/Disable HotPlug support for Root Port */</span><br><span style="color: hsl(120, 100%, 40%);">+    u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   /* USB related */</span><br><span>    struct usb2_port_config usb2_ports[16];</span><br><span>      struct usb3_port_config usb3_ports[10];</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index ccda303..98a1abd 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -165,6 +165,8 @@</span><br><span>                   sizeof(params->PcieRpAdvancedErrorReporting));</span><br><span>    memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,</span><br><span>              sizeof(params->PcieRpLtrEnable));</span><br><span style="color: hsl(120, 100%, 40%);">+   memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,</span><br><span style="color: hsl(120, 100%, 40%);">+           sizeof(params->PcieRpHotPlug));</span><br><span> </span><br><span>        /*</span><br><span>    * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23511">change 23511</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23511"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6 </div>
<div style="display:none"> Gerrit-Change-Number: 23511 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>