<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23484">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/nehalem: Use the common mrc cache driver<br><br>The common mrc cache driver allows to save the raminit training<br>results to a separate fmap region which is more manageable than a<br>cbfsfile.<br><br>Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/nehalem/Kconfig<br>M src/northbridge/intel/nehalem/Makefile.inc<br>M src/northbridge/intel/nehalem/raminit.c<br>3 files changed, 10 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/23484/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig</span><br><span>index 4fdd2bd..5fac263 100644</span><br><span>--- a/src/northbridge/intel/nehalem/Kconfig</span><br><span>+++ b/src/northbridge/intel/nehalem/Kconfig</span><br><span>@@ -20,7 +20,7 @@</span><br><span> select INTEL_EDID</span><br><span> select TSC_MONOTONIC_TIMER</span><br><span> select INTEL_GMA_ACPI</span><br><span style="color: hsl(0, 100%, 40%);">- select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_MRC_SETTINGS</span><br><span> select ACPI_HUGE_LOWMEM_BACKUP</span><br><span> select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span>diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc</span><br><span>index b5c19ff..acb828c 100644</span><br><span>--- a/src/northbridge/intel/nehalem/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/nehalem/Makefile.inc</span><br><span>@@ -29,14 +29,4 @@</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-$(obj)/mrc.cache:</span><br><span style="color: hsl(0, 100%, 40%);">- dd if=/dev/zero count=1 \</span><br><span style="color: hsl(0, 100%, 40%);">- bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \</span><br><span style="color: hsl(0, 100%, 40%);">- tr '\000' '\377' > $@</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cbfs-files-y += mrc.cache</span><br><span style="color: hsl(0, 100%, 40%);">-mrc.cache-file := $(obj)/mrc.cache</span><br><span style="color: hsl(0, 100%, 40%);">-mrc.cache-align := 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">-mrc.cache-type := mrc_cache</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c</span><br><span>index b7b445e..6eb36ef 100644</span><br><span>--- a/src/northbridge/intel/nehalem/raminit.c</span><br><span>+++ b/src/northbridge/intel/nehalem/raminit.c</span><br><span>@@ -43,7 +43,7 @@</span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/intel/speedstep.h></span><br><span> #include <cpu/intel/turbo.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/intel/common/mrc_cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <mrc_cache.h></span><br><span> #endif</span><br><span> </span><br><span> #if !REAL</span><br><span>@@ -90,6 +90,8 @@</span><br><span> u8 largest;</span><br><span> } timing_bounds_t[2][2][2][9];</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_CACHE_VERSION 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct ram_training {</span><br><span> /* [TM][CHANNEL][SLOT][RANK][LANE] */</span><br><span> u16 lane_timings[4][2][2][2][9];</span><br><span>@@ -1740,17 +1742,18 @@</span><br><span> printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8);</span><br><span> </span><br><span> /* Save the MRC S3 restore data to cbmem */</span><br><span style="color: hsl(0, 100%, 40%);">- store_current_mrc_cache(&train, sizeof(train));</span><br><span style="color: hsl(120, 100%, 40%);">+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,</span><br><span style="color: hsl(120, 100%, 40%);">+ &train, sizeof(train));</span><br><span> }</span><br><span> </span><br><span> #if REAL</span><br><span> static const struct ram_training *get_cached_training(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- struct mrc_data_container *cont;</span><br><span style="color: hsl(0, 100%, 40%);">- cont = find_current_mrc_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- if (!cont)</span><br><span style="color: hsl(120, 100%, 40%);">+ struct region_device rdev;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,</span><br><span style="color: hsl(120, 100%, 40%);">+ &rdev))</span><br><span> return 0;</span><br><span style="color: hsl(0, 100%, 40%);">- return (void *)cont->mrc_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)rdev_mmap_full(&rdev);</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23484">change 23484</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251 </div>
<div style="display:none"> Gerrit-Change-Number: 23484 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>