<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23489">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[TEST]mb/lenovo/x220: Use mrc.bin<br><br>Does not work<br><br>Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/lenovo/x220/Kconfig<br>M src/mainboard/lenovo/x220/romstage.c<br>2 files changed, 57 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/23489/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig</span><br><span>index 4b9451b..ad59987 100644</span><br><span>--- a/src/mainboard/lenovo/x220/Kconfig</span><br><span>+++ b/src/mainboard/lenovo/x220/Kconfig</span><br><span>@@ -5,7 +5,7 @@</span><br><span> select SYSTEM_TYPE_LAPTOP</span><br><span> select CPU_INTEL_SOCKET_RPGA989</span><br><span> select NORTHBRIDGE_INTEL_SANDYBRIDGE</span><br><span style="color: hsl(0, 100%, 40%);">- select USE_NATIVE_RAMINIT</span><br><span style="color: hsl(120, 100%, 40%);">+# select USE_NATIVE_RAMINIT</span><br><span> select SOUTHBRIDGE_INTEL_C216</span><br><span> select EC_LENOVO_PMH7</span><br><span> select EC_LENOVO_H8</span><br><span>diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c</span><br><span>index a6c5793..16605f0 100644</span><br><span>--- a/src/mainboard/lenovo/x220/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x220/romstage.c</span><br><span>@@ -27,6 +27,7 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include <console/console.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/raminit.h></span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span>@@ -52,6 +53,56 @@</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_pei_data(struct pei_data *pei_data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pei_data pei_data_template = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pei_version = PEI_VERSION,</span><br><span style="color: hsl(120, 100%, 40%);">+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .epbar = DEFAULT_EPBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .smbusbar = SMBUS_IO_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .wdbbar = 0x4000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .wdbsize = 0x1000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hpet_address = CONFIG_HPET_ADDRESS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcba = (uintptr_t)DEFAULT_RCBABASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pmbase = DEFAULT_PMBASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpiobase = DEFAULT_GPIOBASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .thermalbase = 0xfed08000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .system_type = 0, // 0 Mobile, 1 Desktop/Server</span><br><span style="color: hsl(120, 100%, 40%);">+ .tseg_size = CONFIG_SMM_TSEG_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .spd_addresses = { 0xa0, 0x00,0xa2,0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ .ec_present = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gbe_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ // 0 = leave channel enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ // 1 = disable dimm 0 on channel</span><br><span style="color: hsl(120, 100%, 40%);">+ // 2 = disable dimm 1 on channel</span><br><span style="color: hsl(120, 100%, 40%);">+ // 3 = disable dimm 0+1 on channel</span><br><span style="color: hsl(120, 100%, 40%);">+ .dimm_channel0_disabled = 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dimm_channel1_disabled = 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_ddr3_freq = 1333,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb_port_config = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 0x0040 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 3, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 3, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, 0x0040 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, 0x0040 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 6, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 5, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 6, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 6, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 7, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 6, 0x0080 },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ *pei_data = pei_data_template;</span><br><span style="color: hsl(120, 100%, 40%);">+ // leave onboard dimm address at f0, and copy spd data there.</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 0, 0 },</span><br><span> { 1, 1, 1 },</span><br><span>@@ -82,3 +133,8 @@</span><br><span> void mainboard_config_superio(void)</span><br><span> {</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_should_reset_usb(int s3resume)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !s3resume;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23489">change 23489</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23489"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602 </div>
<div style="display:none"> Gerrit-Change-Number: 23489 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>