<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23483">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">payload/tianocore: Fix patch to preserve coreboot table<br><br>Part of the original patch, commit 85a90e1, reverted edk2 commit:<br>1d7258f [CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTED]<br>which had the unintended effect of causing memory above 2GiB<br>from being unavailable (marked reserved) when booting without a<br>connected display (aka headles mode).<br><br>This commit strips the patch to only the component needed to fix<br>reading of the coreboot table low memory pointer.<br><br>TEST: boot 4GB google/panther without connected display, verify<br>memory above 2GB available via 'dmesg | grep BIOS-e820' and 'free -m'<br><br>Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch<br>1 file changed, 15 insertions(+), 41 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/23483/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch</span><br><span>index 649c6ee..e75052b 100644</span><br><span>--- a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch</span><br><span>+++ b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch</span><br><span>@@ -1,4 +1,4 @@</span><br><span style="color: hsl(0, 100%, 40%);">-From 07742664925f8d055505220258f2589a9c73a80b Mon Sep 17 00:00:00 2001</span><br><span style="color: hsl(120, 100%, 40%);">+From ef89b11ce6f93c96fbd1753a8006dd9c3da212e0 Mon Sep 17 00:00:00 2001</span><br><span> From: ReddestDream <reddestdream@gmail.com></span><br><span> Date: Wed, 3 May 2017 00:13:28 -0400</span><br><span> Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being</span><br><span>@@ -7,46 +7,20 @@</span><br><span> Exclude the bottom 4kb from being included in System Memory HoB</span><br><span> </span><br><span> diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c</span><br><span style="color: hsl(0, 100%, 40%);">-index 262e6b9d7d..da8f060783 100755</span><br><span style="color: hsl(120, 100%, 40%);">+index 262e6b9..d3c5723 100755</span><br><span> --- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c</span><br><span> +++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c</span><br><span style="color: hsl(0, 100%, 40%);">-@@ -246,23 +246,20 @@ CbPeiEntryPoint (</span><br><span style="color: hsl(0, 100%, 40%);">- UINTN PmGpeEnBase;
</span><br><span style="color: hsl(0, 100%, 40%);">- CB_MEM_INFO CbMemInfo;
</span><br><span style="color: hsl(0, 100%, 40%);">- </span><br><span style="color: hsl(0, 100%, 40%);">-- //
</span><br><span style="color: hsl(0, 100%, 40%);">-- // Report lower 640KB of RAM. Attribute EFI_RESOURCE_ATTRIBUTE_TESTED </span><br><span style="color: hsl(0, 100%, 40%);">-- // is intentionally omitted to prevent erasing of the coreboot header </span><br><span style="color: hsl(0, 100%, 40%);">-- // record before it is processed by CbParseMemoryInfo.
</span><br><span style="color: hsl(0, 100%, 40%);">-- //
</span><br><span style="color: hsl(0, 100%, 40%);">- BuildResourceDescriptorHob (
</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_RESOURCE_SYSTEM_MEMORY,
</span><br><span style="color: hsl(0, 100%, 40%);">- (
</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_RESOURCE_ATTRIBUTE_PRESENT |
</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
</span><br><span style="color: hsl(0, 100%, 40%);">-+ EFI_RESOURCE_ATTRIBUTE_TESTED |
</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
</span><br><span style="color: hsl(0, 100%, 40%);">- ),
</span><br><span style="color: hsl(0, 100%, 40%);">-- (EFI_PHYSICAL_ADDRESS)(0),
</span><br><span style="color: hsl(0, 100%, 40%);">-- (UINT64)(0xA0000)
</span><br><span style="color: hsl(0, 100%, 40%);">-+ // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides
</span><br><span style="color: hsl(0, 100%, 40%);">-+ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000),
</span><br><span style="color: hsl(0, 100%, 40%);">-+ (UINT64)(0xA0000 - 0x1000)
</span><br><span style="color: hsl(0, 100%, 40%);">- );
</span><br><span style="color: hsl(0, 100%, 40%);">- </span><br><span style="color: hsl(0, 100%, 40%);">- </span><br><span style="color: hsl(0, 100%, 40%);">-@@ -309,7 +306,7 @@ CbPeiEntryPoint (</span><br><span style="color: hsl(0, 100%, 40%);">- // Set cache on the physical memory
</span><br><span style="color: hsl(0, 100%, 40%);">- //
</span><br><span style="color: hsl(0, 100%, 40%);">- MtrrSetMemoryAttribute (BASE_1MB, LowMemorySize - BASE_1MB, CacheWriteBack);
</span><br><span style="color: hsl(0, 100%, 40%);">-- MtrrSetMemoryAttribute (0, 0xA0000, CacheWriteBack);
</span><br><span style="color: hsl(0, 100%, 40%);">-+ MtrrSetMemoryAttribute ((0 + 0x1000), (0xA0000 - 0x1000), CacheWriteBack);
</span><br><span style="color: hsl(0, 100%, 40%);">- </span><br><span style="color: hsl(0, 100%, 40%);">- //
</span><br><span style="color: hsl(0, 100%, 40%);">- // Create Memory Type Information HOB
</span><br><span>--- </span><br><span style="color: hsl(0, 100%, 40%);">-2.14.0</span><br><span style="color: hsl(120, 100%, 40%);">+@@ -261,8 +261,9 @@ CbPeiEntryPoint (</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ ),</span><br><span style="color: hsl(120, 100%, 40%);">+- (EFI_PHYSICAL_ADDRESS)(0),</span><br><span style="color: hsl(120, 100%, 40%);">+- (UINT64)(0xA0000)</span><br><span style="color: hsl(120, 100%, 40%);">++ // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides</span><br><span style="color: hsl(120, 100%, 40%);">++ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000),</span><br><span style="color: hsl(120, 100%, 40%);">++ (UINT64)(0xA0000 - 0x1000)</span><br><span style="color: hsl(120, 100%, 40%);">+ );</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+2.14.0</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23483">change 23483</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23483"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0 </div>
<div style="display:none"> Gerrit-Change-Number: 23483 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>