<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23477">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/pineview: Use postcar stage to tear down CAR<br><br>This allows to cleanly migrate car globals<br><br>Tested on Intel D510MO, still boots fine.<br><br>Change-Id: I67887b87d8ca2439259c6e1b7349e4d93514194b<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/pineview/Kconfig<br>M src/northbridge/intel/pineview/Makefile.inc<br>M src/northbridge/intel/pineview/ram_calc.c<br>3 files changed, 8 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23477/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig</span><br><span>index e8ef9d9..80f566a 100644</span><br><span>--- a/src/northbridge/intel/pineview/Kconfig</span><br><span>+++ b/src/northbridge/intel/pineview/Kconfig</span><br><span>@@ -29,6 +29,8 @@</span><br><span>     select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span>    select RELOCATABLE_RAMSTAGE</span><br><span>  select INTEL_GMA_ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+  select POSTCAR_CONSOLE</span><br><span> </span><br><span> config BOOTBLOCK_NORTHBRIDGE_INIT</span><br><span>      string</span><br><span>diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc</span><br><span>index a4c08c8..d7936c1 100644</span><br><span>--- a/src/northbridge/intel/pineview/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/pineview/Makefile.inc</span><br><span>@@ -25,4 +25,6 @@</span><br><span> romstage-y += raminit.c</span><br><span> romstage-y += early_init.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>index 63f3942..82073c0 100644</span><br><span>--- a/src/northbridge/intel/pineview/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>@@ -105,8 +105,6 @@</span><br><span>  return (void *) top_of_ram;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* setup_stack_and_mtrrs() determines the stack to use after</span><br><span>  * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span> void *setup_stack_and_mtrrs(void)</span><br><span>@@ -114,7 +112,7 @@</span><br><span>        struct postcar_frame pcf;</span><br><span>    uintptr_t top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+    if (postcar_frame_init(&pcf, 1*KiB))</span><br><span>             die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span>  /* Cache the ROM as WP just below 4GiB. */</span><br><span>@@ -133,8 +131,7 @@</span><br><span>     postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span>       postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">-  * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">-      */</span><br><span style="color: hsl(0, 100%, 40%);">-     return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+        run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+  /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+        return NULL;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23477">change 23477</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23477"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I67887b87d8ca2439259c6e1b7349e4d93514194b </div>
<div style="display:none"> Gerrit-Change-Number: 23477 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>