<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23467">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/car: Compute more things during runtime<br><br>This does a few more things during runtime:<br>* Compute the amount of variable MTRR's during runtime from<br> MTRR_CAP_MSR;<br>* Compute the PHYSMASK_HI during runtime from cpuid;<br>* Rely less on the assembler to get derived values from<br> CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE;<br><br>Tested still boots<br><br>Change-Id: I67d03ad5d612bd5e022e6eb619d988e8ccbf087a<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/cache_as_ram.S<br>1 file changed, 67 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/23467/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/cache_as_ram.S b/src/cpu/intel/car/cache_as_ram.S</span><br><span>index 342e4a5..95d5bfb 100644</span><br><span>--- a/src/cpu/intel/car/cache_as_ram.S</span><br><span>+++ b/src/cpu/intel/car/cache_as_ram.S</span><br><span>@@ -18,13 +18,6 @@</span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* The full cache-as-ram size includes the cache-as-ram portion from coreboot</span><br><span style="color: hsl(0, 100%, 40%);">- * and the space used by the reference code. These 2 values combined should</span><br><span style="color: hsl(0, 100%, 40%);">- * be a power of 2 because the MTRR setup assumes that. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_SIZE \</span><br><span style="color: hsl(0, 100%, 40%);">- (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Cache 4GB - MRC_SIZE_KB for MRC */</span><br><span> #define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)</span><br><span> #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)</span><br><span>@@ -53,18 +46,32 @@</span><br><span> jc wait_for_sipi</span><br><span> </span><br><span> post_code(0x21)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Zero out all fixed range and variable range MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $mtrr_table, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $((mtrr_table_end - mtrr_table) >> 1), %edi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">-clear_mtrrs:</span><br><span style="color: hsl(0, 100%, 40%);">- movw (%esi), %bx</span><br><span style="color: hsl(0, 100%, 40%);">- movzx %bx, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear/disable fixed MTRRs */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $fixed_mtrr_list_size, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+clear_fixed_mtrr:</span><br><span style="color: hsl(120, 100%, 40%);">+ add $-2, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ movzwl fixed_mtrr_list(%ebx), %ecx</span><br><span> wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- add $2, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- dec %edi</span><br><span style="color: hsl(0, 100%, 40%);">- jnz clear_mtrrs</span><br><span style="color: hsl(120, 100%, 40%);">+ jnz clear_fixed_mtrr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Figure put how many MTRRs we have, and clear them out */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $MTRR_CAP_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ movzb %al, %ebx /* Number of variable MTRRs */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+clear_var_mtrr:</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ inc %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ inc %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ dec %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ jnz clear_var_mtrr</span><br><span> </span><br><span> post_code(0x22)</span><br><span> /* Configure the default memory type to uncacheable. */</span><br><span>@@ -74,17 +81,38 @@</span><br><span> wrmsr</span><br><span> </span><br><span> post_code(0x23)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB</span><br><span style="color: hsl(120, 100%, 40%);">+ * based on the physical address size supported for this processor</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0]</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Examples:</span><br><span style="color: hsl(120, 100%, 40%);">+ * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing</span><br><span style="color: hsl(120, 100%, 40%);">+ * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x80000008, %eax /* Address sizes leaf */</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid</span><br><span style="color: hsl(120, 100%, 40%);">+ sub $32, %al</span><br><span style="color: hsl(120, 100%, 40%);">+ movzx %al, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %esi, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ bts %eax, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Set Cache-as-RAM base address. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_BASE(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CONFIG_DCACHE_RAM_BASE, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ or $MTRR_TYPE_WRBACK, %eax</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span> </span><br><span> post_code(0x24)</span><br><span> /* Set Cache-as-RAM mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_MASK(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_MASK(0), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CONFIG_DCACHE_RAM_SIZE, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ dec %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ not %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ or $MTRR_PHYS_MASK_VALID, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %esi, %edx</span><br><span> wrmsr</span><br><span> </span><br><span> post_code(0x25)</span><br><span>@@ -119,9 +147,9 @@</span><br><span> #endif</span><br><span> </span><br><span> /* Clear the cache memory region. This will also fill up the cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CACHE_AS_RAM_BASE, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esi, %edi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CONFIG_DCACHE_RAM_BASE, %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CONFIG_DCACHE_RAM_SIZE, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ shr $0x02, %ecx</span><br><span> // movl $0x23322332, %eax</span><br><span> xorl %eax, %eax</span><br><span> rep stosl</span><br><span>@@ -317,16 +345,16 @@</span><br><span> hlt</span><br><span> jmp .Lhlt</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Fixed MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x250, 0x258, 0x259</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x268, 0x269, 0x26A</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26B, 0x26C, 0x26D</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26E, 0x26F</span><br><span style="color: hsl(0, 100%, 40%);">- /* Variable MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x200, 0x201, 0x202, 0x203</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x204, 0x205, 0x206, 0x207</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x208, 0x209, 0x20A, 0x20B</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x20C, 0x20D, 0x20E, 0x20F</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x210, 0x211, 0x212, 0x213</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table_end:</span><br><span style="color: hsl(120, 100%, 40%);">+fixed_mtrr_list:</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_64K_00000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_16K_80000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_16K_A0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_C0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_C8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_D0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_D8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_E0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_E8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_F0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_F8000</span><br><span style="color: hsl(120, 100%, 40%);">+fixed_mtrr_list_size = . - fixed_mtrr_list</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23467">change 23467</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23467"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I67d03ad5d612bd5e022e6eb619d988e8ccbf087a </div>
<div style="display:none"> Gerrit-Change-Number: 23467 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>