<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23428">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801ix: Use common smm code<br><br>Use common smm code to set up smm and the smihandler.<br><br>Tested on Thinkpad X200.<br><br>Change-Id: Icfdb952ec84b2e8b9a513cfd24dc05d4ee270233<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/i82801ix/Kconfig<br>M src/southbridge/intel/i82801ix/Makefile.inc<br>D src/southbridge/intel/i82801ix/smi.c<br>M src/southbridge/intel/i82801ix/smihandler.c<br>4 files changed, 4 insertions(+), 484 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/23428/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig</span><br><span>index fcf2eb5..1fc7487 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/Kconfig</span><br><span>+++ b/src/southbridge/intel/i82801ix/Kconfig</span><br><span>@@ -25,6 +25,7 @@</span><br><span> select HAVE_SMI_HANDLER</span><br><span> select HAVE_USBDEBUG_OPTIONS</span><br><span> select SOUTHBRIDGE_INTEL_COMMON_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_COMMON_SMM</span><br><span> select HAVE_INTEL_FIRMWARE if !BOARD_EMULATION_QEMU_X86_Q35</span><br><span> </span><br><span> if SOUTHBRIDGE_INTEL_I82801IX</span><br><span>diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc</span><br><span>index 7f30a0b..c688af5 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/i82801ix/Makefile.inc</span><br><span>@@ -32,7 +32,6 @@</span><br><span> ramstage-y += ../i82801gx/reset.c</span><br><span> ramstage-y += ../i82801gx/watchdog.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span> </span><br><span> romstage-y += early_init.c</span><br><span>diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c</span><br><span>deleted file mode 100644</span><br><span>index 38d1578..0000000</span><br><span>--- a/src/southbridge/intel/i82801ix/smi.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,332 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * 2012 secunet Security Networks AG</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/smm/gen1/smi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "i82801ix.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* I945/GM45 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMRAM 0x9d</span><br><span style="color: hsl(0, 100%, 40%);">-#define D_OPEN (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define D_CLS (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define D_LCK (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define G_SMRAME (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* While we read PMBASE dynamically in case it changed, let's</span><br><span style="color: hsl(0, 100%, 40%);">- * initialize it with a sane value</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 pmbase = DEFAULT_PMBASE;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return PM1_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_pm1_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_pm1_status(u16 pm1_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PM1_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_smi_status(u32 smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 27)) printk(BIOS_DEBUG, "GPIO_UNLOCK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return GPE0_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u64 reset_gpe0_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg_h, reg_l;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg_l = inl(pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- reg_h = inl(pmbase + GPE0_STS + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg_l, pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg_h, pmbase + GPE0_STS + 4);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return (((u64)reg_h) << 32) | reg_l;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_gpe0_status(u64 gpe0_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i=31; i>= 16; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear ALT_GP_SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return ALT_GP_SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_alt_gp_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inl(pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i=15; i>= 0; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear TCOx_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return TCOx_STS registers</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tcobase = pmbase + 0x60;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(tcobase + 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_tco_status(u32 tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Set the EOS bit</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void smi_set_eos(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= EOS;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_smm_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 smi_en;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 pm1_en;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Initializing SMM handler...");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_en & GBL_SMI_EN) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SMI# handler already enabled?\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">- dump_smi_status(reset_smi_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_pm1_status(reset_pm1_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_gpe0_status(reset_gpe0_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_alt_gp_smi_status(reset_alt_gp_smi_status());</span><br><span style="color: hsl(0, 100%, 40%);">- dump_tco_status(reset_tco_status());</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable SMI generation:</span><br><span style="color: hsl(0, 100%, 40%);">- * - on TCO events</span><br><span style="color: hsl(0, 100%, 40%);">- * - on APMC writes (io 0xb2)</span><br><span style="color: hsl(0, 100%, 40%);">- * - on writes to GBL_RLS (bios commands)</span><br><span style="color: hsl(0, 100%, 40%);">- * No SMIs:</span><br><span style="color: hsl(0, 100%, 40%);">- * - on microcontroller writes (io 0x62/0x66)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en = 0; /* reset SMI enables */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= TCO_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= APMC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#if DEBUG_PERIODIC_SMIS</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using</span><br><span style="color: hsl(0, 100%, 40%);">- * periodic SMIs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= PERIODIC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= BIOS_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The following need to be on for SMIs to happen */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_en |= EOS | GBL_SMI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- outl(smi_en, pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en |= PWRBTN_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pm1_en |= GBL_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(pm1_en, pmbase + PM1_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_trigger_smi(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /**</span><br><span style="color: hsl(0, 100%, 40%);">- * There are several methods of raising a controlled SMI# via</span><br><span style="color: hsl(0, 100%, 40%);">- * software, among them:</span><br><span style="color: hsl(0, 100%, 40%);">- * - Writes to io 0xb2 (APMC)</span><br><span style="color: hsl(0, 100%, 40%);">- * - Writes to the Local Apic ICR with Delivery mode SMI.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Using the local apic is a bit more tricky. According to</span><br><span style="color: hsl(0, 100%, 40%);">- * AMD Family 11 Processor BKDG no destination shorthand must be</span><br><span style="color: hsl(0, 100%, 40%);">- * used.</span><br><span style="color: hsl(0, 100%, 40%);">- * The whole SMM initialization is quite a bit hardware specific, so</span><br><span style="color: hsl(0, 100%, 40%);">- * I'm not too worried about the better of the methods at the moment</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* raise an SMI interrupt */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, " ... raise SMI#\n");</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x00, 0xb2);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* The GDT or coreboot table is going to live here. But a long time</span><br><span style="color: hsl(0, 100%, 40%);">- * after we relocated the GNVS, so this is not troublesome.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- *(u32 *)0x500 = (u32)gnvs;</span><br><span style="color: hsl(0, 100%, 40%);">- *(u32 *)0x504 = (u32)tcg;</span><br><span style="color: hsl(0, 100%, 40%);">- *(u32 *)0x508 = (u32)smi1;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(APM_CNT_GNVS_UPDATE, 0xb2);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void southbridge_clear_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear SMI status */</span><br><span style="color: hsl(0, 100%, 40%);">- reset_smi_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear PM1 status */</span><br><span style="color: hsl(0, 100%, 40%);">- reset_pm1_status();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set EOS bit so other SMIs can occur. */</span><br><span style="color: hsl(0, 100%, 40%);">- smi_set_eos();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>index 00b6d28..44c3c96 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>+++ b/src/southbridge/intel/i82801ix/smihandler.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span> #include "i82801ix.h"</span><br><span> </span><br><span> #include "nvs.h"</span><br><span>@@ -39,158 +40,9 @@</span><br><span> void *tcg = (void *)0x0;</span><br><span> void *smi1 = (void *)0x0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear PM1_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return PM1_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u16 reset_pm1_status(void)</span><br><span style="color: hsl(120, 100%, 40%);">+u16 get_pmbase(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + PM1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_pm1_status(u16 pm1_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PM1_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear SMI_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return SMI_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_smi_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_smi_status(u32 smi_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMI_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 27)) printk(BIOS_DEBUG, "GPIO_UNLOCK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear GPE0_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return GPE0_STS register</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u64 reset_gpe0_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg_h, reg_l;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg_l = inl(pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- reg_h = inl(pmbase + GPE0_STS + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg_l, pmbase + GPE0_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg_h, pmbase + GPE0_STS + 4);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return (((u64)reg_h) << 32) | reg_l;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_gpe0_status(u64 gpe0_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPE0_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 ");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i=31; i>= 16; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief read and clear TCOx_STS</span><br><span style="color: hsl(0, 100%, 40%);">- * @return TCOx_STS registers</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tcobase = pmbase + 0x60;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(tcobase + 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">- /* set status bits are cleared by writing 1 to them */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & (1 << 18))</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dump_tco_status(u32 tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "TCO_STS: ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return pmbase;</span><br><span> }</span><br><span> </span><br><span> int southbridge_io_trap_handler(int smif)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23428">change 23428</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icfdb952ec84b2e8b9a513cfd24dc05d4ee270233 </div>
<div style="display:none"> Gerrit-Change-Number: 23428 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>