<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23416">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/soraka: Configure unused pins as NC<br><br>This change configures unused pins as not connected.<br><br>Change-Id: I6779d9fba73da8fb2faa08ad5d2236b813105720<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/mainboard/google/poppy/variants/soraka/gpio.c<br>1 file changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/23416/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c</span><br><span>index 50bac4b..0e24bb7 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/soraka/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c</span><br><span>@@ -127,10 +127,10 @@</span><br><span>  PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),</span><br><span>       /* C7  : SM1DATA ==> NC */</span><br><span>        PAD_CFG_NC(GPP_C7),</span><br><span style="color: hsl(0, 100%, 40%);">-     /* C8  : UART0_RXD ==> FP_INT */</span><br><span style="color: hsl(0, 100%, 40%);">-     PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C9  : UART0_TXD ==> FP_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_C9, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C8  : UART0_RXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+       PAD_CFG_NC(GPP_C8),</span><br><span style="color: hsl(120, 100%, 40%);">+   /* C9  : UART0_TXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+       PAD_CFG_NC(GPP_C9),</span><br><span>  /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */</span><br><span>      PAD_CFG_GPO(GPP_C10, 1, DEEP),</span><br><span>       /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */</span><br><span>@@ -170,10 +170,10 @@</span><br><span>       PAD_CFG_NC(GPP_D3),</span><br><span>  /* D4  : FASHTRIG ==> NC */</span><br><span>       PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(0, 100%, 40%);">-     /* D5  : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-  PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-        /* D6  : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-  PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+      /* D5  : ISH_I2C0_SDA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+    PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(120, 100%, 40%);">+   /* D6  : ISH_I2C0_SCL ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+    PAD_CFG_NC(GPP_D6),</span><br><span>  /* D7  : ISH_I2C1_SDA ==> NC */</span><br><span>   PAD_CFG_NC(GPP_D7),</span><br><span>  /* D8  : ISH_I2C1_SCL ==> NC */</span><br><span>@@ -258,7 +258,7 @@</span><br><span>     /* E23 : DDPD_CTRLDATA ==> NC */</span><br><span>  PAD_CFG_NC(GPP_E23),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        /* The next 4 pads are for bit banging the amplifiers, default to I2S */</span><br><span style="color: hsl(120, 100%, 40%);">+      /* The next 3 pads are for bit banging the amplifiers, default to I2S */</span><br><span>     /* F0  : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */</span><br><span>        PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),</span><br><span>         /* F1  : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23416">change 23416</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23416"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6779d9fba73da8fb2faa08ad5d2236b813105720 </div>
<div style="display:none"> Gerrit-Change-Number: 23416 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>