<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23355">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel/fsp: Remove TODOs and make use of EDK2 header<br><br>This patch ensures MemInfoHob.h file can make use of existing UEFI<br>headers as is rather redefine the same structure locally.<br><br>TEST=Download BIOS_Version_122.3 from external github and<br>build MemInfoHob.h without any compilation error.<br><br>Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>1 file changed, 21 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/23355/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index 665e5a0..435eccb</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h</span><br><span>@@ -5,7 +5,7 @@</span><br><span> </span><br><span> @copyright</span><br><span> INTEL CONFIDENTIAL</span><br><span style="color: hsl(0, 100%, 40%);">- Copyright 1999 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright 1999 - 2018 Intel Corporation.</span><br><span> </span><br><span> The source code contained or described herein and all documents related to the</span><br><span> source code ("Material") are owned by Intel Corporation or its suppliers or</span><br><span>@@ -37,6 +37,10 @@</span><br><span> #ifndef _MEM_INFO_HOB_H_</span><br><span> #define _MEM_INFO_HOB_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <Uefi/UefiMultiPhase.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiBootMode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiHob.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #pragma pack (push, 1)</span><br><span> </span><br><span> extern EFI_GUID gSiMemoryS3DataGuid;</span><br><span>@@ -58,25 +62,6 @@</span><br><span> #define B_RANK2_PRS BIT4</span><br><span> #define B_RANK3_PRS BIT5</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// @todo remove and use the MdePkg\Include\Pi\PiHob.h</span><br><span style="color: hsl(0, 100%, 40%);">-#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __HOB__H__</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct _EFI_HOB_GENERIC_HEADER {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 HobType;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 HobLength;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Reserved;</span><br><span style="color: hsl(0, 100%, 40%);">-} EFI_HOB_GENERIC_HEADER;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct _EFI_HOB_GUID_TYPE {</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_HOB_GENERIC_HEADER Header;</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_GUID Name;</span><br><span style="color: hsl(0, 100%, 40%);">- ///</span><br><span style="color: hsl(0, 100%, 40%);">- /// Guid specific data goes here</span><br><span style="color: hsl(0, 100%, 40%);">- ///</span><br><span style="color: hsl(0, 100%, 40%);">-} EFI_HOB_GUID_TYPE;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> ///</span><br><span> /// Defines taken from MRC so avoid having to include MrcInterface.h</span><br><span> ///</span><br><span>@@ -183,6 +168,13 @@</span><br><span> UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.</span><br><span> } MRC_CH_TIMING;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.</span><br><span style="color: hsl(120, 100%, 40%);">+} MRC_TA_TIMING;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ///</span><br><span> /// Memory SMBIOS & OC Memory Data Hob</span><br><span> ///</span><br><span>@@ -208,11 +200,15 @@</span><br><span> } CHANNEL_INFO;</span><br><span> </span><br><span> typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Status; ///< Indicates whether this controller should be used.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 DeviceId; ///< The PCI device id of this memory controller.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RevisionId; ///< The PCI revision id of this memory controller.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.</span><br><span style="color: hsl(0, 100%, 40%);">- CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< Indicates whether this controller should be used.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeviceId; ///< The PCI device id of this memory controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings</span><br><span> } CONTROLLER_INFO;</span><br><span> </span><br><span> typedef struct {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23355">change 23355</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4 </div>
<div style="display:none"> Gerrit-Change-Number: 23355 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>