<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23312">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference code<br><br>Solution: To do an additional config read to the eMMC controller<br>after the controller has been power gated (put to D3)<br><br>Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/acpi/scs.asl<br>1 file changed, 16 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/23312/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl</span><br><span>index e993ddb..b84bedd 100644</span><br><span>--- a/src/soc/intel/cannonlake/acpi/scs.asl</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/scs.asl</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span>  * This file is part of the coreboot project.</span><br><span>  *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation.</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -17,21 +17,33 @@</span><br><span>     /* EMMC */</span><br><span>   Device(PEMC) {</span><br><span>               Name(_ADR, 0x001A0000)</span><br><span style="color: hsl(120, 100%, 40%);">+                Name (TEMP, 0)</span><br><span> </span><br><span>           OperationRegion(SCSR, PCI_Config, 0x00, 0x100)</span><br><span>               Field(SCSR, WordAcc, NoLock, Preserve) {</span><br><span style="color: hsl(0, 100%, 40%);">-                        Offset(0xA2),   // 0xA2, Device PG config</span><br><span style="color: hsl(120, 100%, 40%);">+                     Offset (0x84),  /* PMECTRLSTATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+                   PMCR, 16,</span><br><span style="color: hsl(120, 100%, 40%);">+                     Offset(0xA2),   /* PG_CONFIG */</span><br><span>                      , 2,</span><br><span style="color: hsl(0, 100%, 40%);">-                    PGEN, 1         // [BIT2] PGE - PG Enable</span><br><span style="color: hsl(120, 100%, 40%);">+                     PGEN, 1,        /* PG_ENABLE */</span><br><span>              }</span><br><span> </span><br><span>                Method(_PS0, 0, Serialized) {</span><br><span style="color: hsl(0, 100%, 40%);">-                   Stall (50) // Sleep 50 ms</span><br><span style="color: hsl(120, 100%, 40%);">+                     Stall (50) // Sleep 50 us</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>                  Store(0, PGEN) // Disable PG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+                        /* Set Power State to D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+                   And (PMCR, 0xFFFC, PMCR)</span><br><span style="color: hsl(120, 100%, 40%);">+                      Store (PMCR, ^TEMP)</span><br><span>          }</span><br><span> </span><br><span>                Method(_PS3, 0, Serialized) {</span><br><span>                        Store(1, PGEN) // Enable PG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+                 /* Set Power State to D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+                   Or (PMCR, 0x0003, PMCR)</span><br><span style="color: hsl(120, 100%, 40%);">+                       Store (PMCR, ^TEMP)</span><br><span>          }</span><br><span>    }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23312">change 23312</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23312"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7 </div>
<div style="display:none"> Gerrit-Change-Number: 23312 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>