<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23302">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel: Remove unused CPU code<br><br>Change-Id: I44574e64e621ea60d559d593694af36c648fb7d7<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>D src/cpu/intel/model_f0x/Kconfig<br>D src/cpu/intel/model_f0x/Makefile.inc<br>D src/cpu/intel/model_f0x/model_f0x_init.c<br>D src/cpu/intel/model_f1x/Kconfig<br>D src/cpu/intel/model_f1x/Makefile.inc<br>D src/cpu/intel/model_f1x/model_f1x_init.c<br>D src/cpu/intel/socket_mPGA603/Kconfig<br>D src/cpu/intel/socket_mPGA603/Makefile.inc<br>8 files changed, 0 insertions(+), 139 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/23302/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index bfd8d3a..0000000</span><br><span>--- a/src/cpu/intel/model_f0x/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,8 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config CPU_INTEL_MODEL_F0X</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_BOOTBLOCK_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_VERSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_ROMSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_RAMSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select SMP</span><br><span style="color: hsl(0, 100%, 40%);">- select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span>diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index 158ac21..0000000</span><br><span>--- a/src/cpu/intel/model_f0x/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,3 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += model_f0x_init.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c</span><br><span>deleted file mode 100644</span><br><span>index d942445d..0000000</span><br><span>--- a/src/cpu/intel/model_f0x/model_f0x_init.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,51 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/lapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/microcode.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void model_f0x_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn on caching if we haven't already */</span><br><span style="color: hsl(0, 100%, 40%);">- x86_enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- x86_setup_mtrrs();</span><br><span style="color: hsl(0, 100%, 40%);">- x86_mtrr_check();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Update the microcode */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_update_microcode_from_cbfs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable the local CPU APICs */</span><br><span style="color: hsl(0, 100%, 40%);">- setup_lapic();</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations cpu_dev_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .init = model_f0x_init,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cpu_device_id cpu_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { X86_VENDOR_INTEL, 0x0f07 },</span><br><span style="color: hsl(0, 100%, 40%);">- { X86_VENDOR_INTEL, 0x0f0A },</span><br><span style="color: hsl(0, 100%, 40%);">- { 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cpu_driver driver __cpu_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- .ops = &cpu_dev_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- .id_table = cpu_table,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index cd4cdcf..0000000</span><br><span>--- a/src/cpu/intel/model_f1x/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,8 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config CPU_INTEL_MODEL_F1X</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_BOOTBLOCK_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_VERSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_ROMSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_RAMSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select SMP</span><br><span style="color: hsl(0, 100%, 40%);">- select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span>diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index 81bc161..0000000</span><br><span>--- a/src/cpu/intel/model_f1x/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,3 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += model_f1x_init.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c</span><br><span>deleted file mode 100644</span><br><span>index e0ef3fe..0000000</span><br><span>--- a/src/cpu/intel/model_f1x/model_f1x_init.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,51 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/lapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/microcode.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void model_f1x_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn on caching if we haven't already */</span><br><span style="color: hsl(0, 100%, 40%);">- x86_enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- x86_setup_mtrrs();</span><br><span style="color: hsl(0, 100%, 40%);">- x86_mtrr_check();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Update the microcode */</span><br><span style="color: hsl(0, 100%, 40%);">- intel_update_microcode_from_cbfs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable the local CPU APICs */</span><br><span style="color: hsl(0, 100%, 40%);">- setup_lapic();</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations cpu_dev_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .init = model_f1x_init,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cpu_device_id cpu_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { X86_VENDOR_INTEL, 0x0f12 },</span><br><span style="color: hsl(0, 100%, 40%);">- { X86_VENDOR_INTEL, 0x0f13 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cpu_driver driver __cpu_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- .ops = &cpu_dev_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- .id_table = cpu_table,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/cpu/intel/socket_mPGA603/Kconfig b/src/cpu/intel/socket_mPGA603/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 62e05f6..0000000</span><br><span>--- a/src/cpu/intel/socket_mPGA603/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,5 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config CPU_INTEL_SOCKET_MPGA603</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- select CPU_INTEL_MODEL_F0X</span><br><span style="color: hsl(0, 100%, 40%);">- select CPU_INTEL_MODEL_F1X</span><br><span style="color: hsl(0, 100%, 40%);">- select CPU_INTEL_MODEL_F2X</span><br><span>diff --git a/src/cpu/intel/socket_mPGA603/Makefile.inc b/src/cpu/intel/socket_mPGA603/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index d247f36..0000000</span><br><span>--- a/src/cpu/intel/socket_mPGA603/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,10 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../model_f0x</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../model_f1x</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../model_f2x</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/tsc</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/mtrr</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/lapic</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/cache</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/smm</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../microcode</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../hyperthreading</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23302">change 23302</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I44574e64e621ea60d559d593694af36c648fb7d7 </div>
<div style="display:none"> Gerrit-Change-Number: 23302 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>