<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23255">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/bd82x6x: Reduce function-disable mess<br><br>Most affected boards set the function disabled (FD) register to an<br>arbitrary state dumped from systems running the vendor BIOS. This<br>makes it impossible to enable the devices in devicetree and a pretty<br>big mess of course because nobody cared to keep the register in sync<br>with the devicetree.<br><br>To get completely rid of most of the writes to FD, move setting of<br>PCH_DISABLE_ALWAYS into the southbridge code where it belongs.<br><br>Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/mainboard/apple/macbookair4_2/early_southbridge.c<br>M src/mainboard/asrock/b75pro3-m/romstage.c<br>M src/mainboard/compulab/intense_pc/romstage.c<br>M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c<br>M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c<br>M src/mainboard/google/butterfly/romstage.c<br>M src/mainboard/google/link/romstage.c<br>M src/mainboard/google/parrot/romstage.c<br>M src/mainboard/google/stout/romstage.c<br>M src/mainboard/hp/2570p/romstage.c<br>M src/mainboard/hp/2760p/romstage.c<br>M src/mainboard/hp/8460p/romstage.c<br>M src/mainboard/hp/8470p/romstage.c<br>M src/mainboard/hp/revolve_810_g1/romstage.c<br>M src/mainboard/intel/dcp847ske/early_southbridge.c<br>M src/mainboard/intel/emeraldlake2/romstage.c<br>M src/mainboard/kontron/ktqm77/romstage.c<br>M src/mainboard/lenovo/l520/romstage.c<br>M src/mainboard/lenovo/s230u/romstage.c<br>M src/mainboard/lenovo/t420/romstage.c<br>M src/mainboard/lenovo/t420s/romstage.c<br>M src/mainboard/lenovo/t430/romstage.c<br>M src/mainboard/lenovo/t430s/romstage.c<br>M src/mainboard/lenovo/t520/romstage.c<br>M src/mainboard/lenovo/t530/romstage.c<br>M src/mainboard/lenovo/x131e/romstage.c<br>M src/mainboard/lenovo/x1_carbon_gen1/romstage.c<br>M src/mainboard/lenovo/x220/romstage.c<br>M src/mainboard/lenovo/x230/romstage.c<br>M src/mainboard/roda/rv11/romstage.c<br>M src/mainboard/samsung/lumpy/romstage.c<br>M src/mainboard/samsung/stumpy/romstage.c<br>M src/mainboard/sapphire/pureplatinumh61/romstage.c<br>M src/northbridge/intel/sandybridge/romstage.c<br>M src/northbridge/intel/sandybridge/sandybridge.h<br>M src/southbridge/intel/bd82x6x/early_rcba.c<br>M src/southbridge/intel/bd82x6x/pch.h<br>37 files changed, 46 insertions(+), 113 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/23255/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>index 3388322..b9cfa20 100644</span><br><span>--- a/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>+++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>@@ -41,12 +41,10 @@</span><br><span> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> /* Disable devices. */</span><br><span> RCBA32(0x3414) = 0x00000020;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x3418) = 0x1ffc0ee3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 0, -1 },</span><br><span>diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c</span><br><span>index f556443..645fd08 100644</span><br><span>--- a/src/mainboard/asrock/b75pro3-m/romstage.c</span><br><span>+++ b/src/mainboard/asrock/b75pro3-m/romstage.c</span><br><span>@@ -27,9 +27,8 @@</span><br><span> pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;</span><br><span> }</span><br><span> </span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span>diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>index 4516ac2..6949246 100644</span><br><span>--- a/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>+++ b/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>@@ -47,12 +47,9 @@</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable devices. */</span><br><span> RCBA32(0x3414) = 0x00000000;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x3418) = 0x16e81fe3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 1, 0 },</span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c</span><br><span>index cbc5592..5a2c935 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c</span><br><span>@@ -61,7 +61,7 @@</span><br><span> ite_reg_write(IT8728F_EC, 0x30, 0x01);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> /*</span><br><span> pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);</span><br><span>@@ -131,9 +131,6 @@</span><br><span> RCBA32(0x3844) = 0x0000e5e4;</span><br><span> RCBA32(0x3848) = 0x0000000e;</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x17ee1fe1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable HECI */</span><br><span> RCBA32(FD2) &= ~0x2;</span><br><span> }</span><br><span>diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c</span><br><span>index 22a10ae..a389e68 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c</span><br><span>@@ -61,11 +61,8 @@</span><br><span> ite_reg_write(IT8728F_EC, 0x30, 0x01);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x17ee1fe1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable HECI */</span><br><span> RCBA32(FD2) &= ~0x2;</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c</span><br><span>index 50e037f..3ef4659 100644</span><br><span>--- a/src/mainboard/google/butterfly/romstage.c</span><br><span>+++ b/src/mainboard/google/butterfly/romstage.c</span><br><span>@@ -53,7 +53,7 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span>@@ -101,7 +101,6 @@</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span> /* Disable PCI bridge so MRC does not probe this bus */</span><br><span> reg32 |= PCH_DISABLE_P2P;</span><br><span> RCBA32(FD) = reg32;</span><br><span>diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c</span><br><span>index 733aa30..d0d0f60 100644</span><br><span>--- a/src/mainboard/google/link/romstage.c</span><br><span>+++ b/src/mainboard/google/link/romstage.c</span><br><span>@@ -66,10 +66,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * GFX INTA -> PIRQA (MSI)</span><br><span> * D28IP_P3IP WLAN INTA -> PIRQB</span><br><span>@@ -108,11 +106,6 @@</span><br><span> RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span> (void) RCBA16(OIC);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = reg32;</span><br><span> }</span><br><span> </span><br><span> static uint8_t *locate_spd(void)</span><br><span>diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c</span><br><span>index d9f2f8f..147d4f6 100644</span><br><span>--- a/src/mainboard/google/parrot/romstage.c</span><br><span>+++ b/src/mainboard/google/parrot/romstage.c</span><br><span>@@ -51,7 +51,7 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span>@@ -100,7 +100,6 @@</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span> /* Disable PCI bridge so MRC does not probe this bus */</span><br><span> reg32 |= PCH_DISABLE_P2P;</span><br><span> RCBA32(FD) = reg32;</span><br><span>diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c</span><br><span>index d054b39..2796adb 100644</span><br><span>--- a/src/mainboard/google/stout/romstage.c</span><br><span>+++ b/src/mainboard/google/stout/romstage.c</span><br><span>@@ -57,7 +57,7 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span>@@ -106,7 +106,6 @@</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span> /* Disable PCI bridge so MRC does not probe this bus */</span><br><span> reg32 |= PCH_DISABLE_P2P;</span><br><span> RCBA32(FD) = reg32;</span><br><span>diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c</span><br><span>index 53b44b6..0742543 100644</span><br><span>--- a/src/mainboard/hp/2570p/romstage.c</span><br><span>+++ b/src/mainboard/hp/2570p/romstage.c</span><br><span>@@ -32,9 +32,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;</span><br><span> }</span><br><span> </span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span>diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c</span><br><span>index 0d48f58..c6d9a7c 100644</span><br><span>--- a/src/mainboard/hp/2760p/romstage.c</span><br><span>+++ b/src/mainboard/hp/2760p/romstage.c</span><br><span>@@ -31,9 +31,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;</span><br><span> }</span><br><span> </span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span>diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c</span><br><span>index 7d228e9..0aa9a1a 100644</span><br><span>--- a/src/mainboard/hp/8460p/romstage.c</span><br><span>+++ b/src/mainboard/hp/8460p/romstage.c</span><br><span>@@ -38,9 +38,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;</span><br><span> }</span><br><span> </span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span>diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c</span><br><span>index 2f48aaa..bb9298c 100644</span><br><span>--- a/src/mainboard/hp/8470p/romstage.c</span><br><span>+++ b/src/mainboard/hp/8470p/romstage.c</span><br><span>@@ -37,9 +37,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;</span><br><span> }</span><br><span> </span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span>diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c</span><br><span>index dbf786e..c70660a 100644</span><br><span>--- a/src/mainboard/hp/revolve_810_g1/romstage.c</span><br><span>+++ b/src/mainboard/hp/revolve_810_g1/romstage.c</span><br><span>@@ -37,13 +37,11 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable devices. */</span><br><span> RCBA32(BUC) = 0x00000000;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x17f21feb;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 1, 0 },</span><br><span> { 1, 0, 0 },</span><br><span>diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>index b15f11f..f334157 100644</span><br><span>--- a/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>@@ -41,10 +41,10 @@</span><br><span> pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> /* Disable devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= PCH_DISABLE_ALWAYS | PCH_DISABLE_P2P | PCH_DISABLE_XHCI;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)</span><br><span> /* Enable Gigabit Ethernet */</span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>index 446164f..311022e 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>@@ -63,16 +63,9 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> southbridge_configure_default_intmap();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = reg32;</span><br><span> }</span><br><span> </span><br><span> void mainboard_config_superio(void)</span><br><span>diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c</span><br><span>index 799f17b..2a674a5 100644</span><br><span>--- a/src/mainboard/kontron/ktqm77/romstage.c</span><br><span>+++ b/src/mainboard/kontron/ktqm77/romstage.c</span><br><span>@@ -51,13 +51,12 @@</span><br><span> COMA_LPC_EN | COMB_LPC_EN);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span> /* Disable PCI bridge so MRC does not probe this bus */</span><br><span> reg32 |= PCH_DISABLE_P2P;</span><br><span> RCBA32(FD) = reg32;</span><br><span>diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c</span><br><span>index 84590ae..0f6ffed 100644</span><br><span>--- a/src/mainboard/lenovo/l520/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/l520/romstage.c</span><br><span>@@ -32,12 +32,9 @@</span><br><span> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable devices. */</span><br><span> RCBA32(0x3414) = 0x00000000;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x3418) = 0x00000000;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 0, -1 },</span><br><span>diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c</span><br><span>index 43a3d52..b83eeae 100644</span><br><span>--- a/src/mainboard/lenovo/s230u/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/s230u/romstage.c</span><br><span>@@ -55,12 +55,10 @@</span><br><span> ec_mm_set_bit(0x3b, 4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> /* Disable devices. */</span><br><span> RCBA32(0x3414) = 0x00000020;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x3418) = 0x17f41fe3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 1, 0 },</span><br><span>diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c</span><br><span>index 9f178ea..36e83a3 100644</span><br><span>--- a/src/mainboard/lenovo/t420/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t420/romstage.c</span><br><span>@@ -60,12 +60,11 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x1ea51fe3;</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 1, 0 }, /* P0: system port 4, OC0 */</span><br><span>diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c</span><br><span>index ad49637..55011cf 100644</span><br><span>--- a/src/mainboard/lenovo/t420s/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t420s/romstage.c</span><br><span>@@ -62,10 +62,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x1eb51fe3;</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c</span><br><span>index eb558ac..94679df 100644</span><br><span>--- a/src/mainboard/lenovo/t430/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t430/romstage.c</span><br><span>@@ -57,11 +57,8 @@</span><br><span> (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific, reserved only).</span><br><span style="color: hsl(0, 100%, 40%);">- * FIXME: Test if reserved bits are read only. */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;</span><br><span> }</span><br><span> </span><br><span> /* FIXME: used T530 values here */</span><br><span>diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c</span><br><span>index 89ef10c..3f6d9f2 100644</span><br><span>--- a/src/mainboard/lenovo/t430s/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t430s/romstage.c</span><br><span>@@ -36,10 +36,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x17e81fe3;</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c</span><br><span>index b5ea17c..d6e5edd 100644</span><br><span>--- a/src/mainboard/lenovo/t520/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t520/romstage.c</span><br><span>@@ -76,10 +76,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x1ee51fe3;</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c</span><br><span>index cd2e0e1..f8bb490 100644</span><br><span>--- a/src/mainboard/lenovo/t530/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t530/romstage.c</span><br><span>@@ -64,10 +64,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x17f81fe3;</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c</span><br><span>index 707848b..43e0bd7 100644</span><br><span>--- a/src/mainboard/lenovo/x131e/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x131e/romstage.c</span><br><span>@@ -33,9 +33,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= PCH_DISABLE_ALWAYS;</span><br><span> }</span><br><span> </span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span>diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c</span><br><span>index 5f7b82e..029d867 100644</span><br><span>--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c</span><br><span>@@ -86,7 +86,7 @@</span><br><span> return spd_file + spd_index * 256;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c</span><br><span>index fa52778..a6c5793 100644</span><br><span>--- a/src/mainboard/lenovo/x220/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x220/romstage.c</span><br><span>@@ -47,10 +47,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x1fa41fe3;</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c</span><br><span>index 4d8f330..1a7decc 100644</span><br><span>--- a/src/mainboard/lenovo/x230/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x230/romstage.c</span><br><span>@@ -50,10 +50,8 @@</span><br><span> pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x17f81fe3;</span><br><span> RCBA32(BUC) = 0;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c</span><br><span>index 7219b0b..b36725c 100644</span><br><span>--- a/src/mainboard/roda/rv11/romstage.c</span><br><span>+++ b/src/mainboard/roda/rv11/romstage.c</span><br><span>@@ -16,13 +16,12 @@</span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span> /* Disable unused devices (board specific) */</span><br><span> reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span> /* Disable PCI bridge so MRC does not probe this bus */</span><br><span> reg32 |= PCH_DISABLE_P2P;</span><br><span> RCBA32(FD) = reg32;</span><br><span>diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c</span><br><span>index 3afb196..e22513d 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/romstage.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/romstage.c</span><br><span>@@ -63,10 +63,8 @@</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * GFX INTA -> PIRQA (MSI)</span><br><span> * D28IP_P1IP WLAN INTA -> PIRQB</span><br><span>@@ -107,11 +105,6 @@</span><br><span> RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span> (void) RCBA16(OIC);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = reg32;</span><br><span> }</span><br><span> </span><br><span> static const uint8_t *locate_spd(void)</span><br><span>diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>index ec5368d..6fe6982 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/romstage.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/romstage.c</span><br><span>@@ -75,10 +75,8 @@</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * GFX INTA -> PIRQA (MSI)</span><br><span> * D28IP_P1IP WLAN INTA -> PIRQB</span><br><span>@@ -116,11 +114,6 @@</span><br><span> RCBA16(OIC) = 0x0100;</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span> (void) RCBA16(OIC);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices (board specific) */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = RCBA32(FD);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= PCH_DISABLE_ALWAYS;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = reg32;</span><br><span> }</span><br><span> </span><br><span> static void setup_sio_gpios(void)</span><br><span>diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>index b9a0b8c..a20a1f7 100644</span><br><span>--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>@@ -44,12 +44,10 @@</span><br><span> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span> {</span><br><span> /* Disable devices. */</span><br><span> RCBA32(0x3414) = 0x00000020;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(0x3418) = 0x1fce1fe3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span> const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span> { 1, 0, 0 },</span><br><span>diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c</span><br><span>index 8608d5a..915b1b1 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/romstage.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/romstage.c</span><br><span>@@ -110,7 +110,8 @@</span><br><span> post_code(0x3c);</span><br><span> </span><br><span> southbridge_configure_default_intmap();</span><br><span style="color: hsl(0, 100%, 40%);">- rcba_config();</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_rcba_config();</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_rcba_config();</span><br><span> </span><br><span> post_code(0x3d);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>index dd1a58c..1f56585 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>@@ -220,7 +220,6 @@</span><br><span> </span><br><span> #endif /* !__SMM__ */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void rcba_config(void);</span><br><span> void pch_enable_lpc(void);</span><br><span> void mainboard_early_init(int s3resume);</span><br><span> void mainboard_config_superio(void);</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>index eeecb5f..9bd3a26 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>@@ -63,3 +63,9 @@</span><br><span> /* PCH BWG says to read back the IOAPIC enable register */</span><br><span> (void) RCBA16(OIC);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void</span><br><span style="color: hsl(120, 100%, 40%);">+southbridge_rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) = PCH_DISABLE_ALWAYS;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index 83d9d8d..b094826 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -85,6 +85,8 @@</span><br><span> int early_spi_read(u32 offset, u32 size, u8 *buffer);</span><br><span> void early_thermal_init(void);</span><br><span> void southbridge_configure_default_intmap(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void southbridge_rcba_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void);</span><br><span> void early_pch_init_native(void);</span><br><span> int southbridge_detect_s3_resume(void);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23255">change 23255</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b </div>
<div style="display:none"> Gerrit-Change-Number: 23255 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>