<p>Vaibhav Shankar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23220">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel/cannonlake: Update C-state latency control limits<br><br>PC10 is a necessary condition for S0ix entry. With the current C-state limits,<br>CPU fails to enter PC10 during S0ix. C-state Latency control limits<br>have to be tuned to new values for PC10 entry.<br><br>Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374<br>Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com><br>---<br>M src/soc/intel/cannonlake/cpu.c<br>M src/soc/intel/cannonlake/include/soc/cpu.h<br>2 files changed, 12 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/23220/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c</span><br><span>index 728ab9c..a0797bc 100644</span><br><span>--- a/src/soc/intel/cannonlake/cpu.c</span><br><span>+++ b/src/soc/intel/cannonlake/cpu.c</span><br><span>@@ -136,36 +136,31 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* C-state Interrupt Response Latency Control 0 - package C3 latency */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;</span><br><span> wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);</span><br><span> </span><br><span> /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;</span><br><span> wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);</span><br><span> </span><br><span> /* C-state Interrupt Response Latency Control 3 - package C8 */</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = IRTL_VALID | IRTL_1024_NS |</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS |</span><br><span> C_STATE_LATENCY_CONTROL_3_LIMIT;</span><br><span> wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);</span><br><span> </span><br><span> /* C-state Interrupt Response Latency Control 4 - package C9 */</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = IRTL_VALID | IRTL_1024_NS |</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS |</span><br><span> C_STATE_LATENCY_CONTROL_4_LIMIT;</span><br><span> wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);</span><br><span> </span><br><span> /* C-state Interrupt Response Latency Control 5 - package C10 */</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = IRTL_VALID | IRTL_1024_NS |</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = IRTL_VALID | IRTL_32768_NS |</span><br><span> C_STATE_LATENCY_CONTROL_5_LIMIT;</span><br><span> wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>index bde8f28..dfc7183 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/cpu.h</span><br><span>@@ -21,13 +21,13 @@</span><br><span> #include <device/device.h></span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Latency times in units of 1024ns. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x94</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xfa</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x14c</span><br><span style="color: hsl(0, 100%, 40%);">-#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x3f2</span><br><span style="color: hsl(120, 100%, 40%);">+/* Latency times in units of 32768ns */</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d</span><br><span style="color: hsl(120, 100%, 40%);">+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d</span><br><span> </span><br><span> /* Power in units of mW */</span><br><span> #define C1_POWER 0x3e8</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23220">change 23220</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374 </div>
<div style="display:none"> Gerrit-Change-Number: 23220 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar@intel.com> </div>