<p>Kevin Chiu has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23155">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/fizz: update DPTF settings<br><br>TCPU:<br> _CRT: 100<br> _PSV: 93<br> _TRT: 100/5(s)<br>TSR0:<br> _CRT: 83<br> _PSV: 70<br> _TRT: 100/10(s)<br>TSR1:<br> _CRT: 73<br> _PSV: 67<br> _TRT: 100/30(s)<br><br>PL1:<br> max: 15W<br> min: 3W<br><br>BUG=b:70294260<br>BRANCH=master<br>TEST=build<br>Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935<br>Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com><br>---<br>M src/mainboard/google/fizz/acpi/dptf.asl<br>M src/mainboard/google/fizz/devicetree.cb<br>2 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/23155/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl</span><br><span>index a63142e..f877c71 100644</span><br><span>--- a/src/mainboard/google/fizz/acpi/dptf.asl</span><br><span>+++ b/src/mainboard/google/fizz/acpi/dptf.asl</span><br><span>@@ -14,15 +14,15 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_PASSIVE 85</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_CPU_CRITICAL 99</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 93</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 100</span><br><span> #define DPTF_CPU_ACTIVE_AC0 90</span><br><span> #define DPTF_CPU_ACTIVE_AC1 77</span><br><span> </span><br><span> #define DPTF_TSR0_SENSOR_ID 0</span><br><span> #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR0_PASSIVE 66</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR0_CRITICAL 71</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_PASSIVE 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_CRITICAL 83</span><br><span> #define DPTF_TSR0_ACTIVE_AC0 95</span><br><span> #define DPTF_TSR0_ACTIVE_AC1 85</span><br><span> #define DPTF_TSR0_ACTIVE_AC2 60</span><br><span>@@ -33,18 +33,18 @@</span><br><span> </span><br><span> #define DPTF_TSR1_SENSOR_ID 1</span><br><span> #define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom"</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR1_PASSIVE 65</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR1_CRITICAL 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_PASSIVE 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_CRITICAL 73</span><br><span> </span><br><span> Name (DTRT, Package () {</span><br><span> /* CPU Throttle Effect on CPU */</span><br><span> Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },</span><br><span> </span><br><span> /* CPU Effect on Temp Sensor 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },</span><br><span> </span><br><span> /* CPU Effect on Temp Sensor 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },</span><br><span> })</span><br><span> </span><br><span> Name (MPPC, Package ()</span><br><span>@@ -52,7 +52,7 @@</span><br><span> 0x2, /* Revision */</span><br><span> Package () { /* Power Limit 1 */</span><br><span> 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- 1600, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3000, /* PowerLimitMinimum */</span><br><span> 15000, /* PowerLimitMaximum */</span><br><span> 1000, /* TimeWindowMinimum */</span><br><span> 1000, /* TimeWindowMaximum */</span><br><span>diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb</span><br><span>index c000a54..7b54f74 100644</span><br><span>--- a/src/mainboard/google/fizz/devicetree.cb</span><br><span>+++ b/src/mainboard/google/fizz/devicetree.cb</span><br><span>@@ -267,7 +267,7 @@</span><br><span> </span><br><span> register "speed_shift_enable" = "1"</span><br><span> register "tdp_psyspl2" = "90"</span><br><span style="color: hsl(0, 100%, 40%);">- register "tcc_offset" = "10" # TCC of 90C</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tcc_offset" = "6" # TCC of 94C</span><br><span> </span><br><span> # Use default SD card detect GPIO configuration</span><br><span> register "sdcard_cd_gpio_default" = "GPP_A7"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23155">change 23155</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935 </div>
<div style="display:none"> Gerrit-Change-Number: 23155 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kevin Chiu <Kevin.Chiu@quantatw.com> </div>