<p>Felix Singer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23027">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/solidrun/braswell_som: Initial commit<br><br>Import patch from https://github.com/G33KatWork/Solidrun-Braswell-SOM-Coreboot<br><br>Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b<br>Signed-off-by: Felix Singer <migy@darmstadt.ccc.de><br>---<br>A src/mainboard/solidrun/Kconfig<br>A src/mainboard/solidrun/Kconfig.name<br>A src/mainboard/solidrun/braswell_som/Kconfig<br>A src/mainboard/solidrun/braswell_som/Kconfig.name<br>A src/mainboard/solidrun/braswell_som/Makefile.inc<br>A src/mainboard/solidrun/braswell_som/acpi/ec.asl<br>A src/mainboard/solidrun/braswell_som/acpi/mainboard.asl<br>A src/mainboard/solidrun/braswell_som/acpi/superio.asl<br>A src/mainboard/solidrun/braswell_som/acpi_tables.c<br>A src/mainboard/solidrun/braswell_som/board_info.txt<br>A src/mainboard/solidrun/braswell_som/boardid.c<br>A src/mainboard/solidrun/braswell_som/cmos.layout<br>A src/mainboard/solidrun/braswell_som/com_init.c<br>A src/mainboard/solidrun/braswell_som/devicetree.cb<br>A src/mainboard/solidrun/braswell_som/dsdt.asl<br>A src/mainboard/solidrun/braswell_som/fadt.c<br>A src/mainboard/solidrun/braswell_som/gpio.c<br>A src/mainboard/solidrun/braswell_som/irqroute.c<br>A src/mainboard/solidrun/braswell_som/irqroute.h<br>A src/mainboard/solidrun/braswell_som/onboard.h<br>A src/mainboard/solidrun/braswell_som/ramstage.c<br>A src/mainboard/solidrun/braswell_som/romstage.c<br>A src/mainboard/solidrun/braswell_som/smihandler.c<br>A src/mainboard/solidrun/braswell_som/spd/2Gb.spd.hex<br>A src/mainboard/solidrun/braswell_som/spd/4Gb.spd.hex<br>A src/mainboard/solidrun/braswell_som/spd/8Gb.spd.hex<br>A src/mainboard/solidrun/braswell_som/spd/Makefile.inc<br>A src/mainboard/solidrun/braswell_som/spd/spd.c<br>A src/mainboard/solidrun/braswell_som/w25q64.c<br>29 files changed, 2,062 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/23027/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/solidrun/Kconfig b/src/mainboard/solidrun/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..00532f7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/Kconfig</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if VENDOR_SOLIDRUN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Mainboard model"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/solidrun/*/Kconfig.name"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/solidrun/*/Kconfig"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string "Mainboard Vendor"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "SolidRun"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # VENDOR_SOLIDRUN</span><br><span>diff --git a/src/mainboard/solidrun/Kconfig.name b/src/mainboard/solidrun/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..dc69485</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config VENDOR_SOLIDRUN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "SolidRun"</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/Kconfig b/src/mainboard/solidrun/braswell_som/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..b21e358</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/Kconfig</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_SOLIDRUN_BRASWELLSOM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_8192</span><br><span style="color: hsl(120, 100%, 40%);">+ select ENABLE_BUILTIN_COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_BRASWELL</span><br><span style="color: hsl(120, 100%, 40%);">+ select PCIEXP_L1_SUB_STATE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default solidrun/braswell_som</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Braswell SOM"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "SolidRun"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if !GOP_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_FILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The C0 version of the video bios gets computed from this name</span><br><span style="color: hsl(120, 100%, 40%);">+ so that they can both be added. Only the correct one for the</span><br><span style="color: hsl(120, 100%, 40%);">+ system will be run.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "8086,22b0"</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The VGA_BIOS_ID for the C0 version of the video bios is hardcoded</span><br><span style="color: hsl(120, 100%, 40%);">+ in soc/intel/braswell/Makefile.inc as 8086,22b1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif #GOP_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_SOLIDRUN_BRASWELLSOM</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/Kconfig.name b/src/mainboard/solidrun/braswell_som/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..fde4eef</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SOLIDRUN_BRASWELLSOM</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Braswell SOM"</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/Makefile.inc b/src/mainboard/solidrun/braswell_som/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..244316b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/Makefile.inc</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2016 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += spd</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += boardid.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += irqroute.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ramstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += w25q64.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/acpi/ec.asl b/src/mainboard/solidrun/braswell_som/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/acpi/ec.asl</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/acpi/mainboard.asl b/src/mainboard/solidrun/braswell_som/acpi/mainboard.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..635ff5a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/acpi/mainboard.asl</span><br><span>@@ -0,0 +1,96 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "onboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PWRB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0C"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_SB.PCI0.LPCB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ //#include <drivers/pc80/tpm/acpi/tpm.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//Scope (\_SB.I2C5)</span><br><span style="color: hsl(120, 100%, 40%);">+//{</span><br><span style="color: hsl(120, 100%, 40%);">+// /* Realtek Audio Codec */</span><br><span style="color: hsl(120, 100%, 40%);">+// Device (RTEK) /* Audio Codec driver I2C */</span><br><span style="color: hsl(120, 100%, 40%);">+// {</span><br><span style="color: hsl(120, 100%, 40%);">+// Name (_ADR, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+// Name (_HID, AUDIO_CODEC_HID)</span><br><span style="color: hsl(120, 100%, 40%);">+// Name (_CID, AUDIO_CODEC_CID)</span><br><span style="color: hsl(120, 100%, 40%);">+// Name (_DDN, AUDIO_CODEC_DDN)</span><br><span style="color: hsl(120, 100%, 40%);">+// Name (_UID, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// Method(_CRS, 0x0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+// {</span><br><span style="color: hsl(120, 100%, 40%);">+// Name(SBUF,ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+// {</span><br><span style="color: hsl(120, 100%, 40%);">+// I2CSerialBus(</span><br><span style="color: hsl(120, 100%, 40%);">+// AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */</span><br><span style="color: hsl(120, 100%, 40%);">+// ControllerInitiated, /* SlaveMode: default to ControllerInitiated */</span><br><span style="color: hsl(120, 100%, 40%);">+// 400000, /* ConnectionSpeed: in Hz */</span><br><span style="color: hsl(120, 100%, 40%);">+// AddressingMode7Bit, /* Addressing Mode: default to 7 bit */</span><br><span style="color: hsl(120, 100%, 40%);">+// "\\_SB.I2C5", /* ResourceSource: I2C bus controller name */</span><br><span style="color: hsl(120, 100%, 40%);">+// )</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// /* Jack Detect (index 0) */</span><br><span style="color: hsl(120, 100%, 40%);">+// GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,</span><br><span style="color: hsl(120, 100%, 40%);">+// "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX }</span><br><span style="color: hsl(120, 100%, 40%);">+// } )</span><br><span style="color: hsl(120, 100%, 40%);">+// Return (SBUF)</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// Method (_STA)</span><br><span style="color: hsl(120, 100%, 40%);">+// {</span><br><span style="color: hsl(120, 100%, 40%);">+// Return (0xF)</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span style="color: hsl(120, 100%, 40%);">+//}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_SB.LPEA)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (GBUF, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Jack Detect (index 0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ //GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,</span><br><span style="color: hsl(120, 100%, 40%);">+ // "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX }</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_SB.GPNC)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RBUF, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ //GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,</span><br><span style="color: hsl(120, 100%, 40%);">+ // "\\_SB.GPNC") { BOARD_SCI_GPIO_INDEX }</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RBUF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/acpi/superio.asl b/src/mainboard/solidrun/braswell_som/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..1aeee9a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/acpi/superio.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include "onboard.h"</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/acpi_tables.c b/src/mainboard/solidrun/braswell_som/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..50fe303</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/acpi_tables.c</span><br><span>@@ -0,0 +1,70 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "onboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ memset(gnvs, 0, sizeof(*gnvs));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_init_gnvs(gnvs);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable USB ports in S3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u0 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u1 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable DPTF */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->dpte = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMIC is configured in I2C1, hidden it from OS */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long acpi_fill_madt(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Local APICs */</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_create_madt_lapics(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IOAPIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, IO_APIC_ADDR, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_madt_irq_overrides(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/board_info.txt b/src/mainboard/solidrun/braswell_som/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..0cf00b4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: SolidRun</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Braswell SOM</span><br><span style="color: hsl(120, 100%, 40%);">+Category: sbc</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: n</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/boardid.c b/src/mainboard/solidrun/braswell_som/boardid.c</span><br><span>new file mode 100644</span><br><span>index 0000000..917f464</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/boardid.c</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright(C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t board_id(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ MAYBE_STATIC int id = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return id;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/cmos.layout b/src/mainboard/solidrun/braswell_som/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..ae46e10</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/cmos.layout</span><br><span>@@ -0,0 +1,133 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#start-bit length config config-ID name</span><br><span style="color: hsl(120, 100%, 40%);">+#0 8 r 0 seconds</span><br><span style="color: hsl(120, 100%, 40%);">+#8 8 r 0 alarm_seconds</span><br><span style="color: hsl(120, 100%, 40%);">+#16 8 r 0 minutes</span><br><span style="color: hsl(120, 100%, 40%);">+#24 8 r 0 alarm_minutes</span><br><span style="color: hsl(120, 100%, 40%);">+#32 8 r 0 hours</span><br><span style="color: hsl(120, 100%, 40%);">+#40 8 r 0 alarm_hours</span><br><span style="color: hsl(120, 100%, 40%);">+#48 8 r 0 day_of_week</span><br><span style="color: hsl(120, 100%, 40%);">+#56 8 r 0 day_of_month</span><br><span style="color: hsl(120, 100%, 40%);">+#64 8 r 0 month</span><br><span style="color: hsl(120, 100%, 40%);">+#72 8 r 0 year</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+#80 4 r 0 rate_select</span><br><span style="color: hsl(120, 100%, 40%);">+#84 3 r 0 REF_Clock</span><br><span style="color: hsl(120, 100%, 40%);">+#87 1 r 0 UIP</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+#88 1 r 0 auto_switch_DST</span><br><span style="color: hsl(120, 100%, 40%);">+#89 1 r 0 24_hour_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#90 1 r 0 binary_values_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#91 1 r 0 square-wave_out_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#92 1 r 0 update_finished_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#93 1 r 0 alarm_interrupt_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#94 1 r 0 periodic_interrupt_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#95 1 r 0 disable_clock_updates</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+392 3 e 5 baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+400 1 e 2 hyper_threading</span><br><span style="color: hsl(120, 100%, 40%);">+#401 7 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+#411 5 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: bootloader</span><br><span style="color: hsl(120, 100%, 40%);">+#Used by ChromeOS:</span><br><span style="color: hsl(120, 100%, 40%);">+416 128 r 0 vbnv</span><br><span style="color: hsl(120, 100%, 40%);">+#544 440 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# SandyBridge MRC Scrambler Seed values</span><br><span style="color: hsl(120, 100%, 40%);">+896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(120, 100%, 40%);">+928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+#1000 24 r 0 amd_reserved</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+5 0 115200</span><br><span style="color: hsl(120, 100%, 40%);">+5 1 57600</span><br><span style="color: hsl(120, 100%, 40%);">+5 2 38400</span><br><span style="color: hsl(120, 100%, 40%);">+5 3 19200</span><br><span style="color: hsl(120, 100%, 40%);">+5 4 9600</span><br><span style="color: hsl(120, 100%, 40%);">+5 5 4800</span><br><span style="color: hsl(120, 100%, 40%);">+5 6 2400</span><br><span style="color: hsl(120, 100%, 40%);">+5 7 1200</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 9 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 415 984</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/com_init.c b/src/mainboard/solidrun/braswell_som/com_init.c</span><br><span>new file mode 100644</span><br><span>index 0000000..49c5205</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/com_init.c</span><br><span>@@ -0,0 +1,57 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/lpc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * return family number and internal pad number in that community</span><br><span style="color: hsl(120, 100%, 40%);">+ * by pad number and which community it is in.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* family number in high byte and inner pad number in lowest byte */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void car_mainboard_pre_console_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t *pad_config_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //uint32_t* pad_config_reg_sata_led_n = gpio_pad_config_reg(GP_SOUTHWEST, 43);</span><br><span style="color: hsl(120, 100%, 40%);">+ //write32(pad_config_reg_sata_led_n, 0x18100);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable the UART hardware for COM1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set up the pads to select the UART function</span><br><span style="color: hsl(120, 100%, 40%);">+ * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD</span><br><span style="color: hsl(120, 100%, 40%);">+ * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,</span><br><span style="color: hsl(120, 100%, 40%);">+ M2));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,</span><br><span style="color: hsl(120, 100%, 40%);">+ M2));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/devicetree.cb b/src/mainboard/solidrun/braswell_som/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..25ef542</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/devicetree.cb</span><br><span>@@ -0,0 +1,132 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/braswell</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ############################################################</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set the parameters for MemoryInit</span><br><span style="color: hsl(120, 100%, 40%);">+ ############################################################</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdMrcInitMmioSize" = "0x0800"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdMrcInitSpdAddr1" = "0xa0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdMrcInitSpdAddr2" = "0xa2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdIgdDvmt50PreAlloc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdApertureSize" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdGttSize" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdDvfsEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdCaMirrorEn" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ############################################################</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set the parameters for SiliconInit</span><br><span style="color: hsl(120, 100%, 40%);">+ ############################################################</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdSdcardMode" = "PCH_ACPI_MODE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableHsuart0" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableHsuart1" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableXhci" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableLpe" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableDma0" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableDma1" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableI2C0" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableI2C1" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableI2C2" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableI2C3" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableI2C4" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableI2C5" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableI2C6" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PunitPwrConfigDisable" = "1" # Disable SVID</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ChvSvidConfig" = "SVID_PMIC_CONFIG"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEmmcMode" = "PCH_ACPI_MODE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdUsb3ClkSsc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdDispClkSsc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdSataClkSsc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdEnableSata" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port0PerPortPeTxiSet" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port0PerPortTxiSet" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port0IUsbTxEmphasisEn" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port0PerPortTxPeHalf" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port1PerPortPeTxiSet" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port1PerPortTxiSet" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port1IUsbTxEmphasisEn" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port1PerPortTxPeHalf" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port2PerPortPeTxiSet" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port2PerPortTxiSet" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port2IUsbTxEmphasisEn" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port2PerPortTxPeHalf" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port3PerPortPeTxiSet" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port3PerPortTxiSet" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port3IUsbTxEmphasisEn" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port3PerPortTxPeHalf" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port4PerPortPeTxiSet" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port4PerPortTxiSet" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port4IUsbTxEmphasisEn" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb2Port4PerPortTxPeHalf" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdSataInterfaceSpeed" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdPchSsicEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PMIC_I2CBus" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ISPEnable" = "0" # Disable IUNIT</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ISPPciDevConfig" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdSdDetectChk" = "0" # Disable SD card detect</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # LPE audio codec settings</span><br><span style="color: hsl(120, 100%, 40%);">+ register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable devices in ACPI mode</span><br><span style="color: hsl(120, 100%, 40%);">+ register "lpss_acpi_mode" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_acpi_mode" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sd_acpi_mode" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "lpe_acpi_mode" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Disable SLP_X stretching after SUS power well fail.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "disable_slp_x_stretch_sus_fail" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Allow PCIe devices to wake system from suspend</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_wake_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ # EDS Table 24-4, Figure 24-5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # 8086 2280 - SoC transaction router</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 on end # 8086 22b8 - Camera and Image Processor</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0b.0 on end # 8086 22dc - ?</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 on end # 8086 2294 - MMC Port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # 8086 0F15 - SDIO Port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # 8086 0F16 - SD Port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # 8086 22a3 - Sata controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # 8086 22a8 - LP Engine Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # 8086 22b7 - USB device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # 8086 22c0 - SIO - DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end # 8086 22c1 - I2C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end # 8086 22c2 - I2C Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end # 8086 22c3 - I2C Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.4 on end # 8086 22c4 - I2C Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.5 on end # 8086 22c5 - I2C Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.6 on end # 8086 22c6 - I2C Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.7 on end # 8086 22c7 - I2C Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # 8086 0F04 - HD Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # 8086 2286 - SIO - DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 on end # 8086 0F08 - PWM 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 on end # 8086 0F09 - PWM 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 on end # 8086 228a - HSUART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.4 on end # 8086 228c - HSUART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.5 on end # 8086 228e - SPI 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.6 on end # 8086 2290 - SPI 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.7 on end # 8086 22ac - SPI 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # 8086 229c - LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # 8086 0F12 - SMBus 0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/dsdt.asl b/src/mainboard/solidrun/braswell_som/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..4748f29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/dsdt.asl</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x05, /* DSDT revision: ACPI v5.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", /* OEM id */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", /* OEM table id */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 /* OEM revision */</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Some generic macros */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global NVS and variables */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <acpi/southcluster.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB.PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (RP03)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0002) // _ADR: Address</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion(RPXX, PCI_Config, 0x00, 0x10)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/mainboard.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/fadt.c b/src/mainboard/solidrun/braswell_som/fadt.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9b6f7a9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/fadt.c</span><br><span>@@ -0,0 +1,48 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_header_t *header = &(fadt->header);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->signature, "FACP", 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->length = sizeof(acpi_fadt_t);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->revision = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->oem_id, OEM_ID, 6);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->asl_compiler_id, ASLC, 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->asl_compiler_revision = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->firmware_ctrl = (unsigned long) facs;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->dsdt = (unsigned long) dsdt;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->model = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->preferred_pm_profile = PM_MOBILE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_firmware_ctl_l = (unsigned long)facs;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_firmware_ctl_h = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_dsdt_l = (unsigned long)dsdt;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_dsdt_h = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_fill_in_fadt(fadt);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ header->checksum =</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_checksum((void *) fadt, header->length);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/gpio.c b/src/mainboard/solidrun/braswell_som/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..202c783</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/gpio.c</span><br><span>@@ -0,0 +1,673 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright(C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "irqroute.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "onboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//Clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+// 1. Unused</span><br><span style="color: hsl(120, 100%, 40%);">+// 2. Unused</span><br><span style="color: hsl(120, 100%, 40%);">+// 3. Unused</span><br><span style="color: hsl(120, 100%, 40%);">+// 4. Unused</span><br><span style="color: hsl(120, 100%, 40%);">+// 5. Unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//PWM (Hardware not present, could be used as GPIO):</span><br><span style="color: hsl(120, 100%, 40%);">+// 0 Unconnected</span><br><span style="color: hsl(120, 100%, 40%);">+// 1 Unconnected</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//SDMMC1: eMMC?</span><br><span style="color: hsl(120, 100%, 40%);">+//SDMMC2: Not present</span><br><span style="color: hsl(120, 100%, 40%);">+//SDMMC3: SD-Card on headers</span><br><span style="color: hsl(120, 100%, 40%);">+//FIXME: Check if pullups are necessary</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//LPC: All unconnected</span><br><span style="color: hsl(120, 100%, 40%);">+// AD3 (GPIO): MCU_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+// AD1 (GPIO): MCU_BOOT0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//GPIO_DFX Memory config</span><br><span style="color: hsl(120, 100%, 40%);">+// DFX6</span><br><span style="color: hsl(120, 100%, 40%);">+// DFX7</span><br><span style="color: hsl(120, 100%, 40%);">+// DFX8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* South East Community */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_gpio_map gpse_gpio_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C400: 80 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C410: 80 03 11 00 00 00 C0 05-00 03 13 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C420: 80 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C430: 00 03 13 00 00 00 C0 05-80 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 00 MF_PLT_CLK0 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 01 PWM1 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 02 MF_PLT_CLK1 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 03 MF_PLT_CLK4 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 04 MF_PLT_CLK3 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 05 PWM0*/ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 06 MF_PLT_CLK5 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 07 MF_PLT_CLK2 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE00 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE01 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE02 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE03 */ { .pad_conf0 = 0x00130300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE04 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE05 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE06 */ { .pad_conf0 = 0x00130300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE07 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C800: 81 03 91 00 00 00 C0 05-81 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C810: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C820: 80 03 11 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C830: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C840: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9C850: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 15 SDMMC2_D3_CD_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 16 SDMMC1_CLK */ /* SDMMC1_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ /* SDMMC1_D_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 18 SDMMC2_D1 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 19 SDMMC2_CLK */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 20 SDMMC1_D2 */ /* SDMMC1_D_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 21 SDMMC2_D2 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 22 SDMMC2_CMD */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ /* SDMMC1_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ /* SDMMC1_D_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 25 SDMMC2_D0 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ /* SDMMC1_D_3_CD_B */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE15 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE16 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE17 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE18 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE19 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE20 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE21 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE22 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE23 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE24 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE25 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE26 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ///*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9CC00: 81 03 91 00 00 00 C0 05-80 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9CC10: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9CC20: 81 03 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ //*/</span><br><span style="color: hsl(120, 100%, 40%);">+ //NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ /* SDMMC3_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ //Native_M1, /* 31 SDMMC3_CLK */ /* SDMMC3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ //NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ /* SDMMC3_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ //NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ /* SDMMC3_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ //NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ /* SDMMC3_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ //NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ /* SDMMC3_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE30 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE31 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE32 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE33 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE34 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE35 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D000: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D010: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D020: 00 03 11 00 00 00 C0 05-02 81 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D030: 00 03 11 00 00 00 C0 05-02 81 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 45 MF_LPC_AD2 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 46 LPC_CLKRUNB */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 47 MF_LPC_AD0 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 48 LPC_FRAMEB */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 49 MF_LPC_CLKOUT1 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_OUT_HIGH, /* 50 MF_LPC_AD3 */ /* MCU_RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 51 MF_LPC_CLKOUT0 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_OUT_HIGH, /* 52 MF_LPC_AD1 */ /* MCU_BOOT0 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE45 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE46 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE47 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE48 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE49 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE50 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE51 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE52 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D400: 02 82 91 58 19 00 C0 05-02 81 91 00 00 00 C0 05 *...X............*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D410: 01 82 91 4C 01 00 C0 05-81 03 91 00 00 00 C0 05 *...L............*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D420: 02 81 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D430: 02 81 91 00 00 00 C0 05-81 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D440: 81 03 91 00 00 00 C0 05-80 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPI(trig_edge_low, L5, P_20K_H, non_maskable, en_rx_data, UNMASK_WAKE , NA), /* 60 SPI1_MISO */ /* PMIC_IRQ_1P8 */ /* Open drain? */ /* FIXME: InvRX_Enable - is this connected to the PMIC? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 61 SPI1_CS0_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 62 SPI1_CLK */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 63 MMC1_D6 */ /* MMC1_D6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 64 SPI1_MOSI */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 65 MMC1_D5 */ /* MMC1_D5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_OUT_HIGH, /* 66 SPI1_CS1_B */ /* LAN P0 ISOLATE */ /* FIXME: check if this pin is actually used as P0 Isolate */ //FIXME: Find P1 isolate</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ /* MMC1_D4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU20K(1), /* 68 MMC1_D7 */ /* MMC1_D7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 69 MMC1_RCLK */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE60 */ { .pad_conf0 = 0x58918200, .pad_conf1 = 0x05C00019, .wake_mask = 1, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE61 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE62 */ { .pad_conf0 = 0x4C918201, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE63 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE64 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE65 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE66 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE67 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE68 */ { .pad_conf0 = 0x00910381, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE69 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D800: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D810: 01 82 91 14 01 00 C0 05-00 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D820: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D830: 00 02 91 10 04 00 C0 05-00 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D840: 00 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED9D850: 00 03 11 00 00 00 C0 05-FF FF FF FF FF FF FF FF *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 75 USB_OC1_B */ /* USB_OC1_B */ /* FIXME: pulls? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 76 PMU_RESETBUTTON_B */ /* PMU_RESETBUTTON_B */ /* FIXME: pulls? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 77 GPIO_ALERT */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 78 SDMMC3_PWR_EN_B */ /* SD_CARD_PWRDN_N */ /* FIXME: pulls? */ //FIXME: Connected?</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 79 ILB_SERIRQ */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 80 USB_OC0_B */ /* USB_OC0_B */ /* FIXME: pulls? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ /* SD_CARD_DET_N */ /* FIXME: Native M1, no pull, trig_level, invert */</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPEAKER, /* 82 SPKR */ /* SPKR */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 83 SUSPWRDNACK */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 84 SDMMC1_RCLK */ /* SDMMC1_RCLK */ /* FIXME: no SPARE_PIN!? check if NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 85 SDMMC3_1P8_EN */ /* SD_CARD_PWR_EN */ /* FIXME: check if NC */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE75 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE76 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE77 */ { .pad_conf0 = 0x14918201, .pad_conf1 = 0x05C00001, .wake_mask = 1, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE78 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE79 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE80 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE81 */ { .pad_conf0 = 0x10910300, .pad_conf1 = 0x05C00004, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE82 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE83 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE84 */ { .pad_conf0 = 0x00110380, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SE85 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* South West Community */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_gpio_map gpsw_gpio_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84400: 01 03 91 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84410: 00 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84420: 02 81 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84430: 01 03 91 00 00 00 C0 05-00 81 21 00 00 00 C0 05 *..........!.....*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 00 FST_SPI_D2 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 01 FST_SPI_D0 */ /* SPI_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 02 FST_SPI_CLK */ /* SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 03 FST_SPI_D3 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 04 FST_SPI_CS1_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 05 FST_SPI_D1 */ /* SPI_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 06 FST_SPI_CS0_B */ /* SPI_CS (SPI NOR on SOM) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 07 FST_SPI_CS2_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW00 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW01 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW02 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW03 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW04 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW05 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW06 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW07 */ { .pad_conf0 = 0x00218100, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84800: 00 00 C0 04 00 00 C0 05-01 00 02 00 00 00 C0 04 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84810: 01 03 91 00 00 00 C0 05-00 00 01 00 00 00 C0 04 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84820: 01 03 91 00 00 00 C0 05-01 00 02 00 00 00 C0 04 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84830: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 15 UART1_RTS_B */ /* UART1_RTS_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M2, /* 16 UART1_RXD */ /* UART1_RXD */ //NOTE: set to UART0 for debugging</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 17 UART2_RXD */ /* UART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 18 UART1_CTS_B */ /* UART1_CTS_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 19 UART2_RTS_B */ /* UART2_RTS_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M2, /* 20 UART1_TXD */ /* UART1_TXD */ //NOTE: set to UART0 for debugging</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 21 UART2_TXD */ /* UART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 22 UART2_CTS_B */ /* UART2_CTS_B */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW15 */ GPIO_SKIP, //{ .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW16 */ GPIO_SKIP, //{ .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW17 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW18 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW19 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW20 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW21 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW22 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84C00: 01 03 12 00 00 00 C0 05-01 03 12 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84C10: 00 03 12 00 00 00 C0 05-00 03 12 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84C20: 00 03 11 00 20 00 C0 05-00 03 12 00 00 00 C0 05 *.... ...........*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED84C30: 00 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M2, /* 30 MF_HDA_CLK */ /* MF_HDA_CLK II GP_SSP_0_I2S_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M2, /* 31 GPIO_SW31/MF_HDA_RSTB */ /* AUD_LINK_RST_N || I2S_0_CLK_R_AICO (AIC) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M2, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ /* AUD_LINK_SDI0 (ALC282) || I2S_2_CLK_R_AICO (AIC) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M2, /* 33 MF_HDA_SDO */ /* AUD_LINK_SDO_R||I2S_0_RXD_R_AICO (AIC) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ /* I2S_2_TXD_R_AICO (AIC) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M2, /* 35 MF_HDA_SYNC */ /* AUD_LINKSYNC_R|| I2S_0_FS_R_AICO (AIC) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ /* I2S_2_FS_R_AICO */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 37 MF_HDA_DOCKENB */ /* I2S_2_RXD_R_AICO(AIC) */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW30 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW31 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW32 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW33 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW34 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW35 */ { .pad_conf0 = 0x00120300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW36 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW37 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85000: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85010: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85020: 01 03 91 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85030: 01 03 C1 00 20 00 C0 05-01 03 91 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 45 I2C5_SDA */ /* Touch Panel */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ /* I2C Audio | Touch PAD */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 47 I2C6_SDA */ /* INA Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 48 I2C5_SCL */ /* Touch Panel */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 49 I2C_NFC_SDA */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ /* I2C Audio | Touch PAD */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 51 I2C6_SCL */ /* INA Decice */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 52 I2C_NFC_SCL */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW45 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW46 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW47 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW48 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW49 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW50 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW51 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW52 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85400: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85410: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85420: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85430: 01 03 C1 00 20 00 C0 05-01 03 C1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ /* PMIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 61 I2C0_SDA */ /* 3rd party Sensor Card */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 62 I2C2_SDA */ /* MIPI_CSI CAMERAS, FLASH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ /* PMIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 64 I2C3_SDA */ /* MIPI_CSI CAMERAS, FLASH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 65 I2C0_SCL */ /* 3rd party Sensor Card */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 66 I2C2_SCL */ /* MIPI_CSI CAMERAS, FLASH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 67 I2C3_SCL */ /* MIPI_CSI CAMERAS, FLASH */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW60 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW61 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW62 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW63 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW64 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW65 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW66 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW67 */ { .pad_conf0 = 0x00C10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85800: 00 80 11 00 00 00 C0 05-00 82 C1 0C 11 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85810: 01 03 11 00 00 00 C0 05-00 03 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85820: 01 03 91 00 00 00 C0 05-02 00 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85830: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 75 SATA_GP0 */ /* TOUCH_PNL_RST_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 76 SATA_GP1 */ /* TOUCH_INT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 77 SATA_LEDN */ /* SATA_LED_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 78 SATA_GP2 */ /* SATA_DEVSLP_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 79 MF_SMB_ALERTB */ /* MF_SMB_ALERTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 80 SATA_GP3 */ /* eMMC_RST_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ /* MF_SMB_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* MF_SMB_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW75 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW76 */ { .pad_conf0 = 0x0CC18200, .pad_conf1 = 0x05C00011, .wake_mask = 0, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW77 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW78 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW79 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW80 */ { .pad_conf0 = 0x00110002, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW81 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW82 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85C00: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85C10: 00 03 11 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85C20: 00 03 11 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED85C30: 00 03 11 00 00 00 C0 05-00 03 11 00 20 00 C0 05 *............ ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 90 PCIE_CLKREQ0B */ /* RTL8111G (CLKREQ_N) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 91 PCIE_CLKREQ1B */ /* NGFF(CLKREQ_N) */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 92 GP_SSP_2_CLK */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 93 PCIE_CLKREQ2B */ /* On uSOM NIC CLK Request */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 94 GP_SSP_2_RXD */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 95 PCIE_CLKREQ3B */ /* Tied to Micro SD */ //FIXME: What does this pin do? Is it even a CLKREQ?</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 96 GP_SSP_2_FS */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 97 GP_SSP_2f_TXD */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW90 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW91 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW92 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW93 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW94 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW95 */ { .pad_conf0 = 0x00910300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW96 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*SW97 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* North Community */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_gpio_map gpn_gpio_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+// /*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C400: 02 81 11 00 00 00 C0 05-00 82 01 2C 21 00 C0 05 *...........,!...*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C410: 02 82 91 00 01 80 91 00-00 80 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C420: 02 81 91 00 00 00 C0 05-02 81 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C430: 03 82 91 00 01 80 91 00-00 81 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C440: 03 82 91 00 01 80 91 00-FF FF FF FF FF FF FF FF *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_OUT_HIGH, /* 00 GPIO_DFX0 */ /* LAN P0 RESET */ //FIXME: Is this a reset?</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 01 GPIO_DFX3 */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_INPUT_PU_20K, /* 02 GPIO_DFX7 */ /* RAMID */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 03 GPIO_DFX1 */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 04 GPIO_DFX5 */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 05 GPIO_DFX4 */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_INPUT_PU_20K, /* 06 GPIO_DFX8 */ /* RAMID */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 07 GPIO_DFX2 */ /* ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_INPUT_PU_20K, /* 08 GPIO_DFX6 */ /* RAMID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N00 */ { .pad_conf0 = 0x00118102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N01 */ { .pad_conf0 = 0x2C018200, .pad_conf1 = 0x05C00021, .wake_mask = 0, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N02 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N03 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N04 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N05 */ { .pad_conf0 = 0x00118102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N06 */ { .pad_conf0 = 0x00918203, .pad_conf1 = 0x00918001, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N07 */ { .pad_conf0 = 0x00918202, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N08 */ { .pad_conf0 = 0x00918203, .pad_conf1 = 0x00918001, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// /*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C800: 00 82 01 3C 01 00 C0 05-00 82 11 00 00 00 C0 05 *...<............*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C810: 00 82 11 4C 01 00 C0 05-00 82 91 FC 01 00 C0 05 *...L............*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C820: 01 03 16 00 00 00 C0 05-00 02 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C830: 00 03 11 00 00 00 C0 05-01 03 96 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C840: 00 03 91 00 00 00 C0 05-02 81 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C850: 01 82 91 EC 01 00 C0 05-01 03 A1 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8C860: 00 82 11 00 00 00 C0 05-FF FF FF FF FF FF FF FF *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 15 GPIO_SUS0 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 16 SEC_GPIO_SUS10 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 17 GPIO_SUS3 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ /* GPIO_SUS7 */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M6, /* 19 GPIO_SUS1 */ /* GPIO_SUS1 */ //NOTE: configured as PCI_WAKE1_N, but is just a pin on the headers</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 20 GPIO_SUS5 */ /* GPIO_SUS5 */ //FIXME: What's the native mode of this pin? docs only say strapping pin for Flash Descriptor Security Override</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 21 SEC_GPIO_SUS11 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M6, /* 22 GPIO_SUS4 */ /* */ //Note: configired as PCI_WAKE4_N //FIXME: What's on this pin?</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 23 SEC_GPIO_SUS8 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M6, /* 24 GPIO_SUS2 */ /* GPIO_SUS2 */ //NOTE: configured as PCI_WAKE2_N, but is just a pin on the headers</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 25 GPIO_SUS6 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 26 CX_PREQ_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 27 SEC_GPIO_SUS9 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+ /*N15 */ { .pad_conf0 = 0x3C018200, .pad_conf1 = 0x05C00001, .wake_mask = 1, .int_mask = 1, .gpe = SCI },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N16 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N17 */ { .pad_conf0 = 0x4C118200, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N18 */ { .pad_conf0 = 0xFC918200, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = SMI },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N19 */ { .pad_conf0 = 0x00160301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N20 */ { .pad_conf0 = 0x00910201, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N21 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N22 */ { .pad_conf0 = 0x00960301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N23 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N24 */ { .pad_conf0 = 0x00918102, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N25 */ { .pad_conf0 = 0xEC918201, .pad_conf1 = 0x05C00001, .wake_mask = 0, .int_mask = 1, .gpe = SCI },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N26 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N27 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// /*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8CC00: 01 03 A1 00 00 00 C0 05-00 03 21 00 00 00 C0 05 *..........!.....*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8CC10: 01 03 01 00 60 00 C0 05-00 03 00 00 20 00 C0 05 *....`....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8CC20: 01 03 A1 00 00 00 C0 05-01 03 A1 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8CC30: 00 03 01 00 00 00 C0 05-01 03 A1 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8CC40: 01 03 01 00 40 00 C0 05-00 03 01 00 00 00 C0 05 *....@...........*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8CC50: 00 03 01 00 00 00 C0 05-01 03 A1 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 30 TRST_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 31 TCK */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 32 PROCHOT_B */ /* PROCHOT_B */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_SKIP, /* 33 SVID0_DATA */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 34 TMS */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 35 CX_PRDY_B_2 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 36 TDO_2 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 37 CX_PRDY_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_SKIP, /* 38 SVID0_ALERT_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 39 TDO */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_SKIP, /* 40 SVID0_CLK */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 41 TDI */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N30 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N31 */ { .pad_conf0 = 0x00210300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N32 */ { .pad_conf0 = 0x00010301, .pad_conf1 = 0x05C00060, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N34 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N35 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N36 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N37 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N39 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N41 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// /*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D000: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D010: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D020: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D030: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D040: 02 81 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D050: 00 80 11 00 00 00 C0 05-00 80 11 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 45 GP_CAMERASB05 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 46 GP_CAMERASB02 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 47 GP_CAMERASB08 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 48 GP_CAMERASB00 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 49 GP_CAMERASBO6 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 50 GP_CAMERASB10 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 51 GP_CAMERASB03 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 52 GP_CAMERASB09 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 53 GP_CAMERASB01 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 54 GP_CAMERASB07 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 55 GP_CAMERASB11 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 56 GP_CAMERASB04 */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N45 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N46 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N47 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N48 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N49 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N50 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N51 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N52 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N53 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N54 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N55 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N56 */ { .pad_conf0 = 0x00118000, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+// /*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D400: 00 03 01 00 00 00 C0 05-00 03 11 03 20 00 C0 05 *............ ...*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D410: 01 03 91 00 00 00 C0 04-00 03 01 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D420: 00 03 11 03 20 00 C0 05-00 03 01 00 00 00 C0 05 *.... ...........*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D430: 01 03 92 00 00 00 C0 05-01 03 91 00 00 00 C0 04 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D440: 01 03 11 03 20 00 C0 05-00 03 01 00 00 00 C0 05 *.... ...........*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D450: 00 03 01 00 00 00 C0 05-01 03 92 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// FED8D460: 00 03 01 00 00 00 C0 05-FF FF FF FF FF FF FF FF *................*</span><br><span style="color: hsl(120, 100%, 40%);">+// */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 60 PANEL0_BKLTEN */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 61 HV_DDI0_HPD */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 62 HV_DDI2_DDC_SDA */ /* DDI2_SDA_1P8 */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 63 PANEL1_BKLTCTL */ /* PANEL1_BKLTCTL */</span><br><span style="color: hsl(120, 100%, 40%);">+// NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ /* DDI1_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 65 PANEL0_BKLTCTL */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 66 HV_DDI0_DDC_SDA */ /* DDI0_1_SDA_1P8 */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 67 HV_DDI2_DDC_SCL */ /* DDI2_SCL_1P8 */</span><br><span style="color: hsl(120, 100%, 40%);">+// NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ /* DDI2_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 69 PANEL1_VDDEN */ /* PANEL1_VDDEN */</span><br><span style="color: hsl(120, 100%, 40%);">+// Native_M1, /* 70 PANEL1_BKLTEN */ /* PANEL1_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ /* DDI0_1_SCL_1P8 */</span><br><span style="color: hsl(120, 100%, 40%);">+// GPIO_NC, /* 72 PANEL0_VDDEN */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N60 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N61 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N62 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x04C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N63 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N64 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N65 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N66 */ { .pad_conf0 = 0x00920301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N67 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x04C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N68 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N69 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N70 */ { .pad_conf0 = 0x00010300, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*N71 */ { .pad_conf0 = 0x00920301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* East Community */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_gpio_map gpe_gpio_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94400: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94410: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94420: 01 03 11 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94430: 00 03 11 00 00 00 C0 05-00 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94440: 01 03 91 00 00 00 C0 05-01 03 91 00 00 00 C0 05 *................*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94450: 01 03 C1 00 00 00 C0 05-01 82 91 2C 41 00 C0 05 *...........,A...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 00 PMU_SLP_S3_B */ /* PMU_SLP_S3_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 01 PMU_BATLOW_B */ /* PMU_BATLOW_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 02 SUS_STAT_B */ /* SUS_STAT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 03 PMU_SLP_S0IX_B */ /* SLP_S0IX_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 04 PMU_AC_PRESENT */ /* PMU_AC_PRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 05 PMU_PLTRST_B */ /* PMU_PLTRST_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 06 PMU_SUSCLK */ /* PMU_SUSCLK_1P8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 07 PMU_SLP_LAN_B */ /* */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 08 PMU_PWRBTN_B */ /* PMU_PWRBTN_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Native_M1, /* 09 PMU_SLP_S4_B */ /* PMU_SLP_S4_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ /* PMU_WAKE_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 11 PMU_WAKE_LAN_B */ /* PMU_WAKE_LAN_N */ /* FIXME: Does this connect to onboard RTL8111? */</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+ /*E00 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E01 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E02 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E03 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E04 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E05 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E06 */ { .pad_conf0 = 0x00110301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E07 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E08 */ { .pad_conf0 = 0X00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E09 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E10 */ { .pad_conf0 = 0X00C10301, .pad_conf1 = 0x05C00000, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E11 */ { .pad_conf0 = 0X2C918201, .pad_conf1 = 0X05C00041, .wake_mask = 1, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // /*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94800: 01 03 A1 00 20 00 C0 05-02 81 11 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94810: 01 03 91 00 20 00 C0 05-01 03 A1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94820: 00 81 11 00 20 00 C0 05-01 03 A1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94830: 01 03 A1 00 20 00 C0 05-01 82 91 08 44 00 C0 05 *.... .......D...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94840: 01 03 91 00 20 00 C0 05-01 03 A1 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // FED94850: 00 03 11 00 20 00 C0 05-01 03 91 00 20 00 C0 05 *.... ....... ...*</span><br><span style="color: hsl(120, 100%, 40%);">+ // */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 15 MF_GPIO_3 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 16 MF_GPIO_7 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 17 MF_I2C1_SCL */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 18 MF_GPIO_1 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 19 MF_GPIO_5 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 20 MF_GPIO_9 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 21 MF_GPIO_0 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 22 MF_GPIO_4 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 23 MF_GPIO_8 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 24 MF_GPIO_2 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 25 MF_GPIO_6 */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GPIO_NC, /* 26 MF_I2C1_SDA */ /* */ /* FIXME: NC? Braswell doesn't have an ISH */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E15 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E16 */ { .pad_conf0 = 0x00118102, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E17 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E18 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E19 */ { .pad_conf0 = 0x00118100, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E20 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E21 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E22 */ { .pad_conf0 = 0x08918201, .pad_conf1 = 0x05C00044, .wake_mask = 0, .int_mask = 1, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E23 */ { .pad_conf0 = 0x00910301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E24 */ { .pad_conf0 = 0x00A10301, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E25 */ { .pad_conf0 = 0x00110300, .pad_conf1 = 0x05C00020, .wake_mask = 0, .int_mask = 0, .gpe = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /*E26 */ GPIO_SKIP,</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct soc_gpio_config gpio_config = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* BSW */</span><br><span style="color: hsl(120, 100%, 40%);">+ .north = gpn_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .southeast = gpse_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .southwest = gpsw_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .east = gpe_gpio_map</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_gpio_config *mainboard_get_gpios(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return &gpio_config;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/irqroute.c b/src/mainboard/solidrun/braswell_som/irqroute.c</span><br><span>new file mode 100644</span><br><span>index 0000000..35a8fcc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/irqroute.c</span><br><span>@@ -0,0 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "irqroute.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DEFINE_IRQ_ROUTES;</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/irqroute.h b/src/mainboard/solidrun/braswell_som/irqroute.h</span><br><span>new file mode 100644</span><br><span>index 0000000..c805945</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/irqroute.h</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/irq.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEV_PIRQ_ROUTES \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_PIC_ROUTES \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(A, DISABLE), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(B, DISABLE), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(C, DISABLE), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(D, DISABLE), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(E, DISABLE), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(F, DISABLE), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(G, DISABLE), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(H, DISABLE)</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/onboard.h b/src/mainboard/solidrun/braswell_som/onboard.h</span><br><span>new file mode 100644</span><br><span>index 0000000..bdb674f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/onboard.h</span><br><span>@@ -0,0 +1,52 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef ONBOARD_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define ONBOARD_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "irqroute.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Calculation of gpio based irq.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE</span><br><span style="color: hsl(120, 100%, 40%);">+ * Max direct irq (MAX_DIRECT_IRQ) is 114.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Size of gpio banks are</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPSW_SIZE = 98</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPNC_SIZE = 73</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPEC_SIZE = 27</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPSE_SIZE = 86</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Audio: Gpio index in SW bank */</span><br><span style="color: hsl(120, 100%, 40%);">+//#define JACK_DETECT_GPIO_INDEX 95</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SCI: Gpio index in N bank */</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BOARD_SCI_GPIO_INDEX 15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD CARD gpio */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SDCARD_CD 81</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//#define AUDIO_CODEC_HID "10EC5650"</span><br><span style="color: hsl(120, 100%, 40%);">+//#define AUDIO_CODEC_CID "10EC5650"</span><br><span style="color: hsl(120, 100%, 40%);">+//#define AUDIO_CODEC_DDN "RTEK Codec Controller "</span><br><span style="color: hsl(120, 100%, 40%);">+//#define AUDIO_CODEC_I2C_ADDR 0x1A</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BCRD2_PMIC_I2C_BUS 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/ramstage.c b/src/mainboard/solidrun/braswell_som/ramstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..5b96914</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/ramstage.c</span><br><span>@@ -0,0 +1,67 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "onboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// We configure a few video-related pins using the FSP here, because otherwise Video Init in the FSP seems to fail</span><br><span style="color: hsl(120, 100%, 40%);">+// All other GPIOs are later configured by coreboot routines as defined in gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* N71:HV_DDI0_DDC_SCL >> 0 2 0 00 0xFED8D458 0x00920301 0xFED8D45C 0x05C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N66:HV_DDI0_DDC_SDA >> 0 2 0 00 0xFED8D430 0x00920301 0xFED8D434 0x05C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N61:HV_DDI0_HPD >> 0 1 0 00 0xFED8D408 0x00110300 0xFED8D40C 0x05C00020</span><br><span style="color: hsl(120, 100%, 40%);">+ N64:HV_DDI1_HPD >> 0 1 0 00 0xFED8D420 0x00110301 0xFED8D424 0x05C00020</span><br><span style="color: hsl(120, 100%, 40%);">+ N67:HV_DDI2_DDC_SCL >> 0 1 0 00 0xFED8D438 0x00910301 0xFED8D43C 0x04C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N62:HV_DDI2_DDC_SDA >> 0 1 0 00 0xFED8D410 0x00910301 0xFED8D414 0x04C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N68:HV_DDI2_HPD >> 0 1 0 00 0xFED8D440 0x00110301 0xFED8D444 0x05C00020</span><br><span style="color: hsl(120, 100%, 40%);">+ N65:PANEL0_BKLTCTL >> 0 1 0 00 0xFED8D428 0x00010300 0xFED8D42C 0x05C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N60:PANEL0_BKLTEN >> 0 1 0 00 0xFED8D400 0x00010300 0xFED8D404 0x05C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N72:PANEL0_VDDEN >> 0 1 0 00 0xFED8D460 0x00010300 0xFED8D464 0x05C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N63:PANEL1_BKLTCTL >> 0 1 0 00 0xFED8D418 0x00010300 0xFED8D41C 0x05C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N70:PANEL1_BKLTEN >> 0 1 0 00 0xFED8D450 0x00010300 0xFED8D454 0x05C00000</span><br><span style="color: hsl(120, 100%, 40%);">+ N69:PANEL1_VDDEN >> 0 1 0 00 0xFED8D448 0x00010300 0xFED8D44C 0x05C00000*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NORTH 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static BL_GPIO_PAD_INIT video_gpio_init_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N71:HV_DDI0_DDC_SCL"*/, .Confg0 = 0x00920301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5458, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N66:HV_DDI0_DDC_SDA"*/, .Confg0 = 0x00920301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5430, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N61:HV_DDI0_HPD"*/, .Confg0 = 0x00110300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00020, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5408, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N64:HV_DDI1_HPD"*/, .Confg0 = 0x00110301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00020, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5420, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N67:HV_DDI2_DDC_SCL"*/, .Confg0 = 0x00910301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x04C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5438, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N62:HV_DDI2_DDC_SDA"*/, .Confg0 = 0x00910301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x04C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5410, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N68:HV_DDI2_HPD"*/, .Confg0 = 0x00110301, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00020, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5440, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N65:PANEL0_BKLTCTL"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5428, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N60:PANEL0_BKLTEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5400, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N72:PANEL0_VDDEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5460, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N63:PANEL1_BKLTCTL"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5418, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N70:PANEL1_BKLTEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5450, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL /*L"N69:PANEL1_VDDEN"*/, .Confg0 = 0x00010300, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0x05C00000, .Confg1Changes = 0xFFFFFFFF, .Community = NORTH, .MmioAddr = 0x5448, .Misc = 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { .Name = NULL/*L""*/, .Confg0 = 0xFFFFFFFF, .Confg0Changes = 0xFFFFFFFF, .Confg1 = 0xFFFFFFFF, .Confg1Changes = 0xFFFFFFFF, .Community = 0xFFFFFFFF, .MmioAddr = 0xFFFFFFFF, .Misc = 0xFFFFFFFF },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ChvSvidConfig = SVID_PMIC_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //enable turbo mode</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PcdTurboMode = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //params->GpioFamilyInitTablePtr = ;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->GpioPadInitTablePtr = video_gpio_init_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/romstage.c b/src/mainboard/solidrun/braswell_som/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..5b7e6d2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/romstage.c</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_romstage_entry(struct romstage_params *rp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pei_data *ps = rp->pei_data;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_spd_data(ps);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call back into chipset code with platform values updated. */</span><br><span style="color: hsl(120, 100%, 40%);">+ romstage_common(rp);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(struct romstage_params *params,</span><br><span style="color: hsl(120, 100%, 40%);">+ MEMORY_INIT_UPD *memory_params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update SPD data */</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/smihandler.c b/src/mainboard/solidrun/braswell_som/smihandler.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d2cea20</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/smihandler.c</span><br><span>@@ -0,0 +1,92 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "onboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The wake gpio is SUS_GPIO[0]. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define WAKE_GPIO_EN SUS_GPIO_EN0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_io_trap_handler(int smif)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (smif) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x99:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Sample\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_get_gnvs()->smif = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * On success, the IO Trap Handler returns 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * On failure, the IO Trap Handler returns a value != 0</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * For now, we force the return value to 0 and log all traps to</span><br><span style="color: hsl(120, 100%, 40%);">+ * see what's going on.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ //gnvs->smif = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that</span><br><span style="color: hsl(120, 100%, 40%);">+ * this includes the enable bits in the lower 16 bits.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_gpi(uint32_t alt_gpio_smi)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (alt_gpio_smi & (1 << EC_SMI_GPI)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Process all pending events */</span><br><span style="color: hsl(120, 100%, 40%);">+ while (mainboard_smi_ec() != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_sleep(uint8_t slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB charging if required */</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (slp_typ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case ACPI_S3:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable wake pin in GPE block. */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gpe(WAKE_GPIO_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case ACPI_S5:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_smi_apmc(uint8_t apmc)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (apmc) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case APM_CNT_ACPI_ENABLE:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case APM_CNT_ACPI_DISABLE:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/spd/2Gb.spd.hex b/src/mainboard/solidrun/braswell_som/spd/2Gb.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..0df94d7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/spd/2Gb.spd.hex</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 0B 03 03 11 02 02</span><br><span style="color: hsl(120, 100%, 40%);">+03 00 01 08 0A 00 FE 00</span><br><span style="color: hsl(120, 100%, 40%);">+69 78 69 3C 69 11 18 81</span><br><span style="color: hsl(120, 100%, 40%);">+00 05 3C 3C 01 40 00 01</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 80 AD 01</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/spd/4Gb.spd.hex b/src/mainboard/solidrun/braswell_som/spd/4Gb.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..98c5d2c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/spd/4Gb.spd.hex</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 0B 03 04 19 02 02</span><br><span style="color: hsl(120, 100%, 40%);">+03 00 01 08 0A 00 FE 00</span><br><span style="color: hsl(120, 100%, 40%);">+69 78 69 3C 69 11 18 81</span><br><span style="color: hsl(120, 100%, 40%);">+20 08 3C 3C 01 40 00 01</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 80 AD 01</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/spd/8Gb.spd.hex b/src/mainboard/solidrun/braswell_som/spd/8Gb.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..7dba013</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/spd/8Gb.spd.hex</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 0B 03 05 21 02 02</span><br><span style="color: hsl(120, 100%, 40%);">+03 00 01 08 0A 00 FE 00</span><br><span style="color: hsl(120, 100%, 40%);">+69 78 69 3C 69 11 18 81</span><br><span style="color: hsl(120, 100%, 40%);">+c0 08 3C 3C 01 40 00 01</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 80 AD 01</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/spd/Makefile.inc b/src/mainboard/solidrun/braswell_som/spd/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..fb080f0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/spd/Makefile.inc</span><br><span>@@ -0,0 +1,37 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += spd.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = 2Gb</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += 4Gb</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += 8Gb</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Include spd ROM data</span><br><span style="color: hsl(120, 100%, 40%);">+$(SPD_BIN): $(SPD_DEPS)</span><br><span style="color: hsl(120, 100%, 40%);">+ for f in $+; \</span><br><span style="color: hsl(120, 100%, 40%);">+ do for c in $$(cat $$f | grep -v ^#); \</span><br><span style="color: hsl(120, 100%, 40%);">+ do printf $$(printf '\%o' 0x$$c); \</span><br><span style="color: hsl(120, 100%, 40%);">+ done; \</span><br><span style="color: hsl(120, 100%, 40%);">+ done > $@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-type := spd</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/spd/spd.c b/src/mainboard/solidrun/braswell_som/spd/spd.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ee26ea2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/spd/spd.c</span><br><span>@@ -0,0 +1,198 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <memory_info.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <smbios.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spd.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPD_SIZE 126</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_DFX6_PAD_CFG0 0x4400</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_DFX7_PAD_CFG0 0x4410</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_DFX8_PAD_CFG0 0x4430</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const uint32_t dual_channel_config = (1 << 0) | (1 << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_ramid_gpios(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(COMMUNITY_GPNORTH_BASE + GPIO_DFX6_PAD_CFG0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(COMMUNITY_GPNORTH_BASE + GPIO_DFX7_PAD_CFG0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(COMMUNITY_GPNORTH_BASE + GPIO_DFX8_PAD_CFG0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int ram_id = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ram_id |= get_gpio(COMMUNITY_GPNORTH_BASE, GPIO_DFX6_PAD_CFG0) << 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ram_id |= get_gpio(COMMUNITY_GPNORTH_BASE, GPIO_DFX7_PAD_CFG0) << 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ ram_id |= get_gpio(COMMUNITY_GPNORTH_BASE, GPIO_DFX8_PAD_CFG0) << 2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);</span><br><span style="color: hsl(120, 100%, 40%);">+ //if (ram_id >= total_spds)</span><br><span style="color: hsl(120, 100%, 40%);">+ // return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Determine if this is a single or dual channel memory system */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (1)</span><br><span style="color: hsl(120, 100%, 40%);">+ *dual = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Display the RAM type */</span><br><span style="color: hsl(120, 100%, 40%);">+ //switch (ram_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ //case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ //case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ // printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ // break;</span><br><span style="color: hsl(120, 100%, 40%);">+ //case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ //case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ // printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ // break;</span><br><span style="color: hsl(120, 100%, 40%);">+ //}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Return the serial product data for the RAM */</span><br><span style="color: hsl(120, 100%, 40%);">+ //FIXME: hardcoded to 4Gb dual channel for now</span><br><span style="color: hsl(120, 100%, 40%);">+ return &spd_file_content[SPD_SIZE * /*ram_id*/ 1];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Copy SPD data for on-board memory */</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_spd_data(struct pei_data *ps)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ char *spd_file;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t spd_file_len;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *spd_content;</span><br><span style="color: hsl(120, 100%, 40%);">+ int dual_channel = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Find the SPD data in CBFS. */</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,</span><br><span style="color: hsl(120, 100%, 40%);">+ &spd_file_len);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!spd_file)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("SPD data not found.");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (spd_file_len < SPD_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Missing SPD data.");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_ramid_gpios();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Both channels are always present in SPD data. Always use matched</span><br><span style="color: hsl(120, 100%, 40%);">+ * DIMMs so use the same SPD data for each DIMM.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_content = get_spd_pointer(spd_file,</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_file_len / SPD_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ &dual_channel);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "SPD Data:\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ hexdump(spd_content, SPD_SIZE);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set SPD and memory configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Memory type: 0=DimmInstalled,</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1=SolderDownMemory,</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2=DimmDisabled</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (spd_content != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->spd_data_ch0 = spd_content;</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->spd_ch0_config = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Channel 0 DIMM soldered down\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dual_channel) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Channel 1 DIMM soldered down\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->spd_data_ch1 = spd_content;</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->spd_ch1_config = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Channel 1 DIMM not installed\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->spd_ch1_config = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// static void set_dimm_info(uint32_t chips, uint8_t *spd, struct dimm_info *dimm)</span><br><span style="color: hsl(120, 100%, 40%);">+// {</span><br><span style="color: hsl(120, 100%, 40%);">+// uint16_t clock_frequency;</span><br><span style="color: hsl(120, 100%, 40%);">+// uint32_t log2_chips;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// /* Parse the SPD data to determine the DIMM information */</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm->ddr_type = MEMORY_TYPE_DDR3;</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm->dimm_size = (chips << (spd[4] & 0xf)) << (28 - 3 - 20); /* MiB */</span><br><span style="color: hsl(120, 100%, 40%);">+// clock_frequency = 1000 * spd[11] / (spd[10] * spd[12]); /* MHz */</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm->ddr_frequency = 2 * clock_frequency; /* Double Data Rate */</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm->mod_type = spd[3] & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+// //FIXME: following info is currently not present in SPD data</span><br><span style="color: hsl(120, 100%, 40%);">+// //memcpy((char *)&dimm->module_part_number[0], &spd[0x80],</span><br><span style="color: hsl(120, 100%, 40%);">+// // sizeof(dimm->module_part_number) - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+// //dimm->mod_id = *(uint16_t *)&spd[0x94];</span><br><span style="color: hsl(120, 100%, 40%);">+// switch (chips) {</span><br><span style="color: hsl(120, 100%, 40%);">+// case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+// log2_chips = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+// break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+// log2_chips = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+// break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// case 4:</span><br><span style="color: hsl(120, 100%, 40%);">+// log2_chips = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+// break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// case 8:</span><br><span style="color: hsl(120, 100%, 40%);">+// log2_chips = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+// break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// default:</span><br><span style="color: hsl(120, 100%, 40%);">+// log2_chips = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm->bus_width = (uint8_t)(log2_chips + (spd[7] & 7) + 2 - 3);</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// void mainboard_save_dimm_info(struct romstage_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+// {</span><br><span style="color: hsl(120, 100%, 40%);">+// struct dimm_info *dimm;</span><br><span style="color: hsl(120, 100%, 40%);">+// struct memory_info *mem_info;</span><br><span style="color: hsl(120, 100%, 40%);">+// uint32_t chips;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// /*</span><br><span style="color: hsl(120, 100%, 40%);">+// * Allocate CBMEM area for DIMM information used to populate SMBIOS</span><br><span style="color: hsl(120, 100%, 40%);">+// * table 17</span><br><span style="color: hsl(120, 100%, 40%);">+// */</span><br><span style="color: hsl(120, 100%, 40%);">+// mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));</span><br><span style="color: hsl(120, 100%, 40%);">+// printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);</span><br><span style="color: hsl(120, 100%, 40%);">+// if (mem_info == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+// return;</span><br><span style="color: hsl(120, 100%, 40%);">+// memset(mem_info, 0, sizeof(*mem_info));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// /* Describe the first channel memory */</span><br><span style="color: hsl(120, 100%, 40%);">+// chips = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm = &mem_info->dimm[0];</span><br><span style="color: hsl(120, 100%, 40%);">+// set_dimm_info(chips, params->pei_data->spd_data_ch0, dimm);</span><br><span style="color: hsl(120, 100%, 40%);">+// mem_info->dimm_cnt = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// /* Describe the second channel memory */</span><br><span style="color: hsl(120, 100%, 40%);">+// if (params->pei_data->spd_ch1_config == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm = &mem_info->dimm[1];</span><br><span style="color: hsl(120, 100%, 40%);">+// set_dimm_info(chips, params->pei_data->spd_data_ch1, dimm);</span><br><span style="color: hsl(120, 100%, 40%);">+// dimm->channel_num = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+// mem_info->dimm_cnt = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span style="color: hsl(120, 100%, 40%);">+// }</span><br><span>diff --git a/src/mainboard/solidrun/braswell_som/w25q64.c b/src/mainboard/solidrun/braswell_som/w25q64.c</span><br><span>new file mode 100644</span><br><span>index 0000000..075a0d0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/solidrun/braswell_som/w25q64.c</span><br><span>@@ -0,0 +1,72 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Andreas Galauner <andreas@galauner.de></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPI lockdown configuration W25Q64FW.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_0 0x01 /* Write, no address */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_1 0x03 /* Write, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_2 0x03 /* READ: Read Data */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_2 0x02 /* Read, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_3 0x00 /* Read, no address */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_4 0x03 /* Write, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_5 0x00 /* Read, no address */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_6 0x03 /* Write, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE_7 0x02 /* Read, address required */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct spi_config spi_config = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .preop = SPI_OPPREFIX,</span><br><span style="color: hsl(120, 100%, 40%);">+ .optype = SPI_OPTYPE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },</span><br><span style="color: hsl(120, 100%, 40%);">+ .lvscc = SPI_VSCC,</span><br><span style="color: hsl(120, 100%, 40%);">+ .uvscc = SPI_VSCC,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_get_spi_config(struct spi_config *cfg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ //memcpy(cfg, &spi_config, sizeof(*cfg));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23027">change 23027</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23027"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b </div>
<div style="display:none"> Gerrit-Change-Number: 23027 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Singer <migy@darmstadt.ccc.de> </div>