<p>Kane Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23018">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Add device setting for sata power optimization<br><br>This change provides option in devicetree and feeds the option to<br>FSP SataPwrOptEnable UPD for power saving purpose<br><br>BUG=b:70491485<br><br>Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b<br>Signed-off-by: Kane Chen <kane.chen@intel.com><br>---<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>2 files changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/23018/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 00088b9..4e8cb81 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -542,6 +542,9 @@</span><br><span> </span><br><span>      /* PCH Trip Temperature */</span><br><span>   u8 pch_trip_temp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* Enable/Disable Sata power optimization */</span><br><span style="color: hsl(120, 100%, 40%);">+  u8 SataPwrOptEnable;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_skylake_config config_t;</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 24a239e..ccda303 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -219,6 +219,7 @@</span><br><span>       params->SataEnable = config->EnableSata;</span><br><span>       params->SataMode = config->SataMode;</span><br><span>   params->SataSpeedLimit = config->SataSpeedLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+        params->SataPwrOptEnable = config->SataPwrOptEnable;</span><br><span> </span><br><span>       tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;</span><br><span>       tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23018">change 23018</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23018"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b </div>
<div style="display:none"> Gerrit-Change-Number: 23018 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kane Chen <kane.chen@intel.com> </div>