<p>Gergely Kiss has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23002">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/asus/am1i-a: add support for board ASUS AM1I-A<br><br>Adding code to support the board ASUS AM1I-A.<br>Tested with multiple payloads and OSes with satisfactory results.<br>Details are going to be published on the board's status page.<br><br>Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7<br>Signed-off-by: Gergely Kiss <mail.gery@gmail.com><br>---<br>A src/mainboard/asus/am1i-a/BiosCallOuts.c<br>A src/mainboard/asus/am1i-a/Kconfig<br>A src/mainboard/asus/am1i-a/Kconfig.name<br>A src/mainboard/asus/am1i-a/Makefile.inc<br>A src/mainboard/asus/am1i-a/OemCustomize.c<br>A src/mainboard/asus/am1i-a/OptionsIds.h<br>A src/mainboard/asus/am1i-a/acpi/AmdImc.asl<br>A src/mainboard/asus/am1i-a/acpi/flag0.asl<br>A src/mainboard/asus/am1i-a/acpi/gpe.asl<br>A src/mainboard/asus/am1i-a/acpi/ide.asl<br>A src/mainboard/asus/am1i-a/acpi/mainboard.asl<br>A src/mainboard/asus/am1i-a/acpi/routing.asl<br>A src/mainboard/asus/am1i-a/acpi/sata.asl<br>A src/mainboard/asus/am1i-a/acpi/si.asl<br>A src/mainboard/asus/am1i-a/acpi/sio.asl<br>A src/mainboard/asus/am1i-a/acpi/sleep.asl<br>A src/mainboard/asus/am1i-a/acpi/superio.asl<br>A src/mainboard/asus/am1i-a/acpi/thermal.asl<br>A src/mainboard/asus/am1i-a/acpi/usb_oc.asl<br>A src/mainboard/asus/am1i-a/acpi_tables.c<br>A src/mainboard/asus/am1i-a/board_info.txt<br>A src/mainboard/asus/am1i-a/buildOpts.c<br>A src/mainboard/asus/am1i-a/cmos.default<br>A src/mainboard/asus/am1i-a/cmos.layout<br>A src/mainboard/asus/am1i-a/devicetree.cb<br>A src/mainboard/asus/am1i-a/dsdt.asl<br>A src/mainboard/asus/am1i-a/irq_tables.c<br>A src/mainboard/asus/am1i-a/mainboard.c<br>A src/mainboard/asus/am1i-a/mptable.c<br>A src/mainboard/asus/am1i-a/romstage.c<br>30 files changed, 2,897 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/23002/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c</span><br><span>new file mode 100644</span><br><span>index 0000000..77eba92</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c</span><br><span>@@ -0,0 +1,149 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "AGESA.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/agesa/BiosCallOuts.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/agesa/state_machine.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "FchPlatform.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cbfs.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const BIOS_CALLOUT_STRUCT BiosCallouts[] =</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_DO_RESET, agesa_Reset },</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_READ_SPD, agesa_ReadSpd },</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * CODEC Initialization Table for Azalia HD Audio using Realtek ALC887-VD chip (from linux, running under vendor bios)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const CODEC_ENTRY Alc887_VerbTbl[] =</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x11, 0x40330000 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x12, 0x411111f0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x14, 0x01014010 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x15, 0x411111f0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x16, 0x411111f0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x17, 0x411111f0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x18, 0x01a19030 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x19, 0x02a19040 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x1a, 0x0181303f },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x1b, 0x02214020 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x1c, 0x411111f0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x1d, 0x4024c601 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x1e, 0x411111f0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x1f, 0x411111f0 }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const CODEC_TBL_LIST CodecTableList[] =</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x10ec0662, (CODEC_ENTRY*)&Alc887_VerbTbl[0]},</span><br><span style="color: hsl(120, 100%, 40%);">+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_INTERNAL_DIODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_TEMP0 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_TEMP1 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_TEMP2 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_TEMP3 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_TEMP0_FILTER 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_ZERO 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_INPUT_DISABLED 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_AUTOMODE (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_LINEARMODE (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_STEPMODE ~(1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_POLARITY_HIGH (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAN_POLARITY_LOW ~(1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_28KHZ 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_25KHZ 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_23KHZ 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_21KHZ 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_29KHZ 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_18KHZ 0x5</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_100HZ 0xF7</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_87HZ 0xF8</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_58HZ 0xF9</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_44HZ 0xFA</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_35HZ 0xFB</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_29HZ 0xFC</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_22HZ 0xFD</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_14HZ 0xFE</span><br><span style="color: hsl(120, 100%, 40%);">+#define FREQ_11HZ 0xFF</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_reset->Mode = 6;</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read SATA speed setting from CMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ enum cb_err ret;</span><br><span style="color: hsl(120, 100%, 40%);">+ ret = get_option(&FchParams_reset->SataSetMaxGen2, "sata_speed");</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ret != CB_SUCCESS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_reset->SataSetMaxGen2 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Azalia Controller OEM Codec Table Pointer */</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fan Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_env->Imc.ImcEnable = FALSE;</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_env->Hwm.HwMonitorEnable = FALSE;</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read SATA controller mode from CMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ enum cb_err ret;</span><br><span style="color: hsl(120, 100%, 40%);">+ ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode");</span><br><span style="color: hsl(120, 100%, 40%);">+ if ( ret != CB_SUCCESS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_env->Sata.SataClass = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch ((SATA_CLASS)FchParams_env->Sata.SataClass) { // code from olivehillplus (ft3b) - only one place where sata is configured</span><br><span style="color: hsl(120, 100%, 40%);">+ case SataLegacyIde:</span><br><span style="color: hsl(120, 100%, 40%);">+ case SataRaid:</span><br><span style="color: hsl(120, 100%, 40%);">+ case SataAhci:</span><br><span style="color: hsl(120, 100%, 40%);">+ case SataAhci7804:</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_env->Sata.SataIdeMode = FALSE;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "AHCI or RAID or IDE = %x\n", FchParams_env->Sata.SataClass);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ case SataIde2Ahci:</span><br><span style="color: hsl(120, 100%, 40%);">+ case SataIde2Ahci7804:</span><br><span style="color: hsl(120, 100%, 40%);">+ default: /* SataNativeIde */</span><br><span style="color: hsl(120, 100%, 40%);">+ FchParams_env->Sata.SataIdeMode = TRUE;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "IDE2AHCI = %x\n", FchParams_env->Sata.SataClass);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..c9a94af</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/Kconfig</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_ASUS_AM1I_A</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_8192</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_AMD_AGESA_FAMILY16_KB</span><br><span style="color: hsl(120, 100%, 40%);">+ select FORCE_AM1_SOCKET_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ select GFXUMA</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select USE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_PIRQ_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_MP_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_AMD_AGESA_YANGTZE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_ITE_IT8623E</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default asus/am1i-a</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "AM1I-A"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HW_MEM_HOLE_SIZEK</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x200000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HW_MEM_HOLE_SIZE_AUTO_INC</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config IRQ_SLOT_COUNT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config ONBOARD_VGA_IS_PRIMARY</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "1002,9836"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HUDSON_LEGACY_FREE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_ASUS_AM1I_A</span><br><span>diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..840e821</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_ASUS_AM1I_A</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "AM1I-A"</span><br><span>diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..f8895fa</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/Makefile.inc</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += buildOpts.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += BiosCallOuts.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += OemCustomize.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += buildOpts.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += BiosCallOuts.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += OemCustomize.c</span><br><span>diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c</span><br><span>new file mode 100644</span><br><span>index 0000000..80528c3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/OemCustomize.c</span><br><span>@@ -0,0 +1,157 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "AGESA.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <PlatformMemoryConfiguration.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/agesa/state_machine.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_PORT_DESCRIPTOR PortList[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmDisabled, 0x01, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmDisabled, 0x02, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmDisabled, 0x03, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmDisabled, 0x04, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmDisabled, 0x05, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_DDI_DESCRIPTOR DdiList[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DP0 to HDMI0/DP */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DP1 to FCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DP2 to HDMI1/DP */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .Flags = DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .SocketId = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .PciePortList = PortList,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DdiLinkList = DdiList</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ FchReset->SataEnable = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ FchReset->IdeEnable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*----------------------------------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+ * CUSTOMER OVERIDES MEMORY TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ *----------------------------------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA</span><br><span style="color: hsl(120, 100%, 40%);">+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable</span><br><span style="color: hsl(120, 100%, 40%);">+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will</span><br><span style="color: hsl(120, 100%, 40%);">+ * use its default conservative settings.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SEED_A 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+ HW_RXEN_SEED(</span><br><span style="color: hsl(120, 100%, 40%);">+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,</span><br><span style="color: hsl(120, 100%, 40%);">+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,</span><br><span style="color: hsl(120, 100%, 40%);">+ SEED_A),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ MOTHER_BOARD_LAYERS(LAYERS_4),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),</span><br><span style="color: hsl(120, 100%, 40%);">+ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */</span><br><span style="color: hsl(120, 100%, 40%);">+ ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),</span><br><span style="color: hsl(120, 100%, 40%);">+ CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PSO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */</span><br><span style="color: hsl(120, 100%, 40%);">+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/OptionsIds.h b/src/mainboard/asus/am1i-a/OptionsIds.h</span><br><span>new file mode 100644</span><br><span>index 0000000..eaf2442</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/OptionsIds.h</span><br><span>@@ -0,0 +1,59 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * @file</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDS Option File</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is used to switch on/off IDS features.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _OPTION_IDS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _OPTION_IDS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file generates the defaults tables for the Integrated Debug Support</span><br><span style="color: hsl(120, 100%, 40%);">+ * Module. The documented build options are imported from a user controlled</span><br><span style="color: hsl(120, 100%, 40%);">+ * file for processing. The build options for the Integrated Debug Support</span><br><span style="color: hsl(120, 100%, 40%);">+ * Module are listed below:</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDSOPT_IDS_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDSOPT_ERROR_TRAP_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDSOPT_CONTROL_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDSOPT_TRACING_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDSOPT_PERF_ANALYSIS</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDSOPT_ASSERT_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDS_DEBUG_PORT</span><br><span style="color: hsl(120, 100%, 40%);">+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ **/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDSOPT_IDS_ENABLED TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDSOPT_CONTROL_ENABLED TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDSOPT_TRACING_ENABLED TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDSOPT_PERF_ANALYSIS TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDSOPT_ASSERT_ENABLED TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#undef IDSOPT_DEBUG_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDSOPT_DEBUG_ENABLED FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+//#undef IDSOPT_HOST_SIMNOW</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDSOPT_HOST_SIMNOW FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+//#undef IDSOPT_HOST_HDT</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDSOPT_HOST_HDT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define IDS_DEBUG_PORT 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/AmdImc.asl b/src/mainboard/asus/am1i-a/acpi/AmdImc.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..aa941ba</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/AmdImc.asl</span><br><span>@@ -0,0 +1,110 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//BTDC Due to IMC Fan, ACPI control codes</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+Field(IMIO , ByteAcc, NoLock, Preserve) {</span><br><span style="color: hsl(120, 100%, 40%);">+ IMCX,8,</span><br><span style="color: hsl(120, 100%, 40%);">+ IMCA,8</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x80),</span><br><span style="color: hsl(120, 100%, 40%);">+ MSTI, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ MITS, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRG0, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRG1, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRG2, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRG3, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(WACK, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ While (LNotEqual(Local0, 0xFA)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(MRG0, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Sleep(10)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//Init</span><br><span style="color: hsl(120, 100%, 40%);">+Method (ITZE, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xB5, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x96, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x80, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(MRG2, 0x01, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Local0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x81, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//Sleep</span><br><span style="color: hsl(120, 100%, 40%);">+Method (IMSP, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xB5, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x96, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(1, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x98, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xB4, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x96, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//Wake</span><br><span style="color: hsl(120, 100%, 40%);">+Method (IMWK, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xB5, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x96, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x80, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(MRG2, 0x01, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, MRG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Local0, MRG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x81, MSTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ WACK()</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/flag0.asl b/src/mainboard/asus/am1i-a/acpi/flag0.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..ca3b4fd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/flag0.asl</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Field (GRAM, ByteAcc, Lock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x10),</span><br><span style="color: hsl(120, 100%, 40%);">+ FLG0, 8</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/gpe.asl b/src/mainboard/asus/am1i-a/acpi/gpe.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..9a84698</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/gpe.asl</span><br><span>@@ -0,0 +1,74 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope(\_GPE) { /* Start Scope GPE */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* General event 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L03) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L00\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Legacy PM event */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L08) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L08\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Temp warning (TWarn) event */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L09) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L09\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Notify (\_TZ.TZ00, 0x80) */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB controller PME# */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L0B) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L0B\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ExtEvent0 SCI event */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L10) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L10\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ExtEvent1 SCI event */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L11) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L11\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO0 or GEvent8 event */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L18) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L18\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Azalia SCI event */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L1B) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_GPE\\_L1B\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope GPE */</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/ide.asl b/src/mainboard/asus/am1i-a/acpi/ide.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..52d85ab</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/ide.asl</span><br><span>@@ -0,0 +1,245 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* No IDE functionality */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(PCI0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(IDEC) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0x00140001)</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "ide.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Some timing tables */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UDTT, Package(){ /* Udma timing table */</span><br><span style="color: hsl(120, 100%, 40%);">+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name(MDTT, Package(){ /* MWDma timing table */</span><br><span style="color: hsl(120, 100%, 40%);">+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name(POTT, Package(){ /* Pio timing table */</span><br><span style="color: hsl(120, 100%, 40%);">+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Some timing register value tables */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(MDRT, Package(){ /* MWDma timing register table */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PORT, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ Field(ICRG, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ PPTS, 8, /* Primary PIO Slave Timing */</span><br><span style="color: hsl(120, 100%, 40%);">+ PPTM, 8, /* Primary PIO Master Timing */</span><br><span style="color: hsl(120, 100%, 40%);">+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */</span><br><span style="color: hsl(120, 100%, 40%);">+ PMTM, 8, /* Primary MWDMA Master Timing */</span><br><span style="color: hsl(120, 100%, 40%);">+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ PPSM, 4, /* Primary PIO slave Mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ PDSM, 4, /* Primary UltraDMA Mode */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(GTTM, 1) /* get total time*/</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */</span><br><span style="color: hsl(120, 100%, 40%);">+ Increment(Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */</span><br><span style="color: hsl(120, 100%, 40%);">+ Increment(Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(Multiply(30, Add(Local0, Local1)))</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device(PRID)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_GTM, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ NAME(OTBF, Buffer(20) { /* out buffer */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Just return if the channel is disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ If(And(PPCR, 0x01)) { /* primary PIO control */</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(OTBF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Always tell them independent timing available and IOChannelReady used on both drives */</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(BFFG, 0x1A, BFFG)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* save total time of primary PIO master timing to PIO spd0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(GTTM(PPTM), PSD0)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* save total time of primary PIO slave Timing to PIO spd1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(GTTM(PPTS), PSD1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(BFFG, 0x01, BFFG)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(BFFG, 0x04, BFFG)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(OTBF) /* out buffer */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Method(_GTM) */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_STM, 3, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ NAME(INBF, Buffer(20) { /* in buffer */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Divide(Local0, 7, PDMM,)</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(PDCR, 0x01, PDCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(DerefOf(Index(MDRT, Local0)), PMTM)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Divide(Local0, 7, PDSM,)</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(PDCR, 0x02, PDCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(DerefOf(Index(MDRT, Local0)), PMTS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Return(INBF) */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /*End Method(_STM) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(MST)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_GTF) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(CMBF, Buffer(21) {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 1, POMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 8, DMMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 5, CMDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 12, CMDB)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 19, CMDC)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xA0, CMDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xA0, CMDB)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xA0, CMDC)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(PPMM, 0x08, POMD)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If(And(PDCR, 0x01)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(PDMM, 0x40, DMMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match</span><br><span style="color: hsl(120, 100%, 40%);">+ (MDTT, MLE, GTTM(PMTM),</span><br><span style="color: hsl(120, 100%, 40%);">+ MTR, 0, 0), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ If(LLess(Local0, 3)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(0x20, Local0, DMMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(CMBF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Device(MST) */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(SLAV)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_GTF) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(CMBF, Buffer(21) {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 1, POMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 8, DMMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 5, CMDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 12, CMDB)</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateByteField(CMBF, 19, CMDC)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xB0, CMDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xB0, CMDB)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0xB0, CMDC)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(PPSM, 0x08, POMD)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If(And(PDCR, 0x02)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(PDSM, 0x40, DMMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Match</span><br><span style="color: hsl(120, 100%, 40%);">+ (MDTT, MLE, GTTM(PMTS),</span><br><span style="color: hsl(120, 100%, 40%);">+ MTR, 0, 0), Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ If(LLess(Local0, 3)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Or(0x20, Local0, DMMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(CMBF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End Device(SLAV) */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/mainboard.asl b/src/mainboard/asus/am1i-a/acpi/mainboard.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..68609d8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/mainboard.asl</span><br><span>@@ -0,0 +1,35 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory related values */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PBLN, 0x0) /* Length of BIOS area */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(HPBA, 0xFED00000) /* Base address of HPET table */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Some global data */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(OSV, Ones) /* Assume nothing */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PMOD, One) /* Assume APIC */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* AcpiGpe0Blk */</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field(GP0B, ByteAcc, NoLock, Preserve) {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 11,</span><br><span style="color: hsl(120, 100%, 40%);">+ USBS, 1,</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/routing.asl b/src/mainboard/asus/am1i-a/acpi/routing.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..7cb7a2f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/routing.asl</span><br><span>@@ -0,0 +1,193 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001</span><br><span style="color: hsl(120, 100%, 40%);">+ )</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "routing.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Routing is in System Bus scope */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PR0, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NB devices */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 0 - F16 Host Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 0, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 1, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 0, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 1, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 2, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 3, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FCH devices */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 0, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 1, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 2, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 3, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0012FFFF, 0, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0012FFFF, 1, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0013FFFF, 0, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0013FFFF, 1, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 0, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 1, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0010FFFF, 0, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0010FFFF, 1, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 17 - SATA controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0011FFFF, 0, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name(APR0, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NB devices in APIC mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 0 - F15 Host Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 0, 0, 44 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 1, 0, 45 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 2 - PCIe Bridges */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 0, 0, 24 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 1, 0, 25 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 2, 0, 26 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 3, 0, 27 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SB devices in APIC mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 2, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 3, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0012FFFF, 0, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0012FFFF, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0013FFFF, 0, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0013FFFF, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 0, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0010FFFF, 0, 0, 0x12},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0010FFFF, 1, 0, 0x11},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus 0, Dev 17 - SATA controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0011FFFF, 0, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PS2, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+Name(APS2, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GFX */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PS4, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+Name(APS4, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe slot - Hooked to PCIe slot 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, 0, 24 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, 0, 25 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, 0, 26 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, 0, 27 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PS5, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+Name(APS5, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, 0, 28 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, 0, 29 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, 0, 30 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, 0, 31 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PS6, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+Name(APS6, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, 0, 32 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, 0, 33 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, 0, 34 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, 0, 35 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PS7, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+Name(APS7, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, 0, 36 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, 0, 37 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, 0, 38 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, 0, 39 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(PS8, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, INTA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, INTB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, INTC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, INTD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+Name(APS8, Package(){</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 0, 0, 40 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 1, 0, 41 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 2, 0, 42 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0000FFFF, 3, 0, 43 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/sata.asl b/src/mainboard/asus/am1i-a/acpi/sata.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..c8cf86d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/sata.asl</span><br><span>@@ -0,0 +1,144 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(PCI0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(SATA) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0x00110000)</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "sata.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name(STTM, Buffer(20) {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1f, 0x00, 0x00, 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Start by clearing the PhyRdyChg bits */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_INI) {</span><br><span style="color: hsl(120, 100%, 40%);">+ \_GPE._L1F()</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device(PMRY)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_GTM, 0x0, NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(STTM)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_STM, 0x3, NotSerialized) {}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(PMST) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_STA,0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(P0IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x0F) /* sata is visible */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ else {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x00) /* sata is missing */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }/* end of PMST */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(PSLA)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_STA,0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(P1IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x0F) /* sata is visible */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ else {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x00) /* sata is missing */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* end of PSLA */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* end of PMRY */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device(SEDY)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 1) /* IDE Scondary Channel */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_GTM, 0x0, NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(STTM)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_STM, 0x3, NotSerialized) {}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(SMST)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_STA,0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(P2IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x0F) /* sata is visible */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ else {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x00) /* sata is missing */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* end of SMST */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(SSLA)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_ADR, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_STA,0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(P3IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x0F) /* sata is visible */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ else {</span><br><span style="color: hsl(120, 100%, 40%);">+ return (0x00) /* sata is missing */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* end of SSLA */</span><br><span style="color: hsl(120, 100%, 40%);">+} /* end of SEDY */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA Hot Plug Support */</span><br><span style="color: hsl(120, 100%, 40%);">+Scope(\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_L1F,0x0,NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (\_SB.P0PR) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(\_SB.P0IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ sleep(32)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */</span><br><span style="color: hsl(120, 100%, 40%);">+ store(one, \_SB.P0PR)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (\_SB.P1PR) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(\_SB.P1IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ sleep(32)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */</span><br><span style="color: hsl(120, 100%, 40%);">+ store(one, \_SB.P1PR)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (\_SB.P2PR) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(\_SB.P2IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ sleep(32)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */</span><br><span style="color: hsl(120, 100%, 40%);">+ store(one, \_SB.P2PR)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (\_SB.P3PR) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (LGreater(\_SB.P3IS,0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ sleep(32)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */</span><br><span style="color: hsl(120, 100%, 40%);">+ store(one, \_SB.P3PR)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/si.asl b/src/mainboard/asus/am1i-a/acpi/si.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2923471</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/si.asl</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope(\_SI) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_SST, 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_SI\\_SST\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO(" New Indicator state: ") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO(Arg0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Scope SI */</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/sio.asl b/src/mainboard/asus/am1i-a/acpi/sio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b423af5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/sio.asl</span><br><span>@@ -0,0 +1,87 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (IOID, SystemIO, 0x2E, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (IOID, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x07),</span><br><span style="color: hsl(120, 100%, 40%);">+ LDN, 8, /* Logical Device Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x20),</span><br><span style="color: hsl(120, 100%, 40%);">+ CID1, 8, /* Chip ID Byte 1, 0x87 */</span><br><span style="color: hsl(120, 100%, 40%);">+ CID2, 8, /* Chip ID Byte 2, 0x12 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x30),</span><br><span style="color: hsl(120, 100%, 40%);">+ ACTR, 8, /* Function activate */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xF0),</span><br><span style="color: hsl(120, 100%, 40%);">+ APC0, 8, /* APC/PME Event Enable Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ APC1, 8, /* APC/PME Status Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ APC2, 8, /* APC/PME Control Register 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ APC3, 8, /* Environment Controller Special Configuration Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ APC4, 8 /* APC/PME Control Register 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enter the 8728 Config */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (EPNP)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x87, SIOI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x01, SIOI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x55, SIOI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x55, SIOI)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Exit the 8728 Config */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (XPNP)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x02, SIOI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x02, SIOD)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Keyboard PME is routed to SB700 Gevent3. We can wake</span><br><span style="color: hsl(120, 100%, 40%);">+ * up the system by pressing the key.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+Method (SIOS, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We only enable KBD PME for S5. */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LLess (Arg0, 0x05))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ EPNP()</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("8728F\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x4, LDN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (One, ACTR) /* Enable EC */</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x4, LDN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x04, APC4)</span><br><span style="color: hsl(120, 100%, 40%);">+ */ /* falling edge. which mode? Not sure. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x4, LDN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x4, LDN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */</span><br><span style="color: hsl(120, 100%, 40%);">+ XPNP()</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+Method (SIOW, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ EPNP()</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x4, LDN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, APC0) /* disable keyboard PME */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0x4, LDN)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0xFF, APC1) /* clear keyboard PME status */</span><br><span style="color: hsl(120, 100%, 40%);">+ XPNP()</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/sleep.asl b/src/mainboard/asus/am1i-a/acpi/sleep.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..1225a62</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/sleep.asl</span><br><span>@@ -0,0 +1,93 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Wake status package */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(WKST,Package(){Zero, Zero})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+* \_PTS - Prepare to Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+* Arg0=The value of the sleeping state S1=1, S2=2, etc</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+* -none-</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* The _PTS control method is executed at the beginning of the sleep process</span><br><span style="color: hsl(120, 100%, 40%);">+* for S1-S5. The sleeping value is passed to the _PTS control method. This</span><br><span style="color: hsl(120, 100%, 40%);">+* control method may be executed a relatively long time before entering the</span><br><span style="color: hsl(120, 100%, 40%);">+* sleep state and the OS may abort the operation without notification to</span><br><span style="color: hsl(120, 100%, 40%);">+* the ACPI driver. This method cannot modify the configuration or power</span><br><span style="color: hsl(120, 100%, 40%);">+* state of any device in the system.</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+External(\_SB.APTS, MethodObj)</span><br><span style="color: hsl(120, 100%, 40%);">+External(\_SB.AWAK, MethodObj)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS, 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_PTS\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("From S0 to S") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO(Arg0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear wake status structure. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, Index(WKST,0))</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0, Index(WKST,1))</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(7, UPWS)</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.APTS(Arg0)</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Method(\_PTS) */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+* \_BFS OEM Back From Sleep method</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+* Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+* -none-</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+Method(\_BFS, 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_BFS\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("From S") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO(Arg0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO(" to S0\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+* \_WAK System Wake method</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* Entry:</span><br><span style="color: hsl(120, 100%, 40%);">+* Arg0=The value of the sleeping state S1=1, S2=2</span><br><span style="color: hsl(120, 100%, 40%);">+*</span><br><span style="color: hsl(120, 100%, 40%);">+* Exit:</span><br><span style="color: hsl(120, 100%, 40%);">+* Return package of 2 DWords</span><br><span style="color: hsl(120, 100%, 40%);">+* Dword 1 - Status</span><br><span style="color: hsl(120, 100%, 40%);">+* 0x00000000 wake succeeded</span><br><span style="color: hsl(120, 100%, 40%);">+* 0x00000001 Wake was signaled but failed due to lack of power</span><br><span style="color: hsl(120, 100%, 40%);">+* 0x00000002 Wake was signaled but failed due to thermal condition</span><br><span style="color: hsl(120, 100%, 40%);">+* Dword 2 - Power Supply state</span><br><span style="color: hsl(120, 100%, 40%);">+* if non-zero the effective S-state the power supply entered</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+Method(\_WAK, 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("\\_WAK\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO("From S") */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO(Arg0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DBGO(" to S0\n") */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(1,USBS)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.AWAK(Arg0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(WKST)</span><br><span style="color: hsl(120, 100%, 40%);">+} /* End Method(\_WAK) */</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/superio.asl b/src/mainboard/asus/am1i-a/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..d3144e5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/superio.asl</span><br><span>@@ -0,0 +1,125 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Scope is \_SB.PCI0.LPCB</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Values, defined here, must match settings in devicetree.cb</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (PS2M) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0F13"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {12}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ And (FLG0, 0x04, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Local0, 0x04)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0F)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (PS2K) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0303"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ And (FLG0, 0x04, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Local0, 0x04)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0F)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {1}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (COM1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0501"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ And (FLG0, 0x04, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Local0, 0x04)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0F)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {4}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {4}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (COM2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0501"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ And (FLG0, 0x04, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Local0, 0x04)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0F)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {3}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {3}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LPT1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0401"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ And (FLG0, 0x04, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (Local0, 0x04)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0F)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0378, 0x0378, 0x04, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0778, 0x0778, 0x04, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {5}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0378, 0x378, 0x04, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0778, 0x778, 0x04, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {5}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/thermal.asl b/src/mainboard/asus/am1i-a/acpi/thermal.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/thermal.asl</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi/usb_oc.asl b/src/mainboard/asus/am1i-a/acpi/usb_oc.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..42785f8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi/usb_oc.asl</span><br><span>@@ -0,0 +1,128 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* simple name description */</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001</span><br><span style="color: hsl(120, 100%, 40%);">+ )</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "usb.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB overcurrent mapping pins. */</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM0, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM1, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM2, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM3, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM4, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM5, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM6, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM7, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM8, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+Name(UOM9, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Overcurrent GPEs */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if 0 /* TODO: Update for am1ml */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(UCOC, 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Sleep(20)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0x13,CMTI)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(0,GPSL)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 0 overcurrent uses Gpm 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+If(LLessEqual(UOM0,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L13) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 1 overcurrent uses Gpm 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM1,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L14) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 2 overcurrent uses Gpm 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM2,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L15) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 3 overcurrent uses Gpm 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM3,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L16) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 4 overcurrent uses Gpm 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM4,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L19) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 5 overcurrent uses Gpm 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM5,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L1A) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 6 overcurrent uses Gpm 6 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM6,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Method (_L1C) { */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L06) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 7 overcurrent uses Gpm 7 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM7,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Method (_L1D) { */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L07) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 8 overcurrent uses Gpm 8 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM8,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L17) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB Port 9 overcurrent uses Gpm 9 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (LLessEqual(UOM9,9)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_GPE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_L0E) {</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4779313</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/acpi_tables.c</span><br><span>@@ -0,0 +1,52 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long acpi_fill_madt(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* create all subtables for processors */</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_create_madt_lapics(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Write Yangtze IOAPIC, only one */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,</span><br><span style="color: hsl(120, 100%, 40%);">+ IO_APIC_ADDR, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Remove the hardcode */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFEC20000, 24);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(120, 100%, 40%);">+ current, 0, 0, 2, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(120, 100%, 40%);">+ current, 0, 9, 9, 0xF);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 0: mean bus 0--->ISA */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 0: PIC 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 2: APIC 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 5 mean: 0101 --> Edge-triggered, Active high */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* create all subtables for processors */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1: LINT1 connect to NMI */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/board_info.txt b/src/mainboard/asus/am1i-a/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..4873e82</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/board_info.txt</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: mini</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://www.asus.com/us/Motherboards/AM1IA/</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: DIP8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: y</span><br><span>diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c</span><br><span>new file mode 100644</span><br><span>index 0000000..5e9b0d6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/buildOpts.c</span><br><span>@@ -0,0 +1,342 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * @file</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * AMD User options selection for a Brazos platform solution system</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is placed in the user's platform directory and contains the</span><br><span style="color: hsl(120, 100%, 40%);">+ * build option selections desired for that platform.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * For Information about this file, see @ref platforminstall.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "AGESA.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_FT3_SOCKET_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_G34_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_C32_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_FS1_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_FM1_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_FP2_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_FT1_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_AM3_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INSTALL_FM2_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef INSTALL_FT3_SOCKET_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ #define INSTALL_FT3_SOCKET_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_SRAT FALSE //TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_SLIT FALSE //TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_WHEA FALSE //TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_CRAT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_CDIT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDOPT_REMOVE_DMI TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//This element selects whether P-States should be forced to be independent,</span><br><span style="color: hsl(120, 100%, 40%);">+// as reported by the ACPI _PSD object. For single-link processors,</span><br><span style="color: hsl(120, 100%, 40%);">+// setting TRUE for OS to support this feature.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+/* Build configuration values here.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_CURRENT_LIMIT 15000</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_SLEW_RATE 10000</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PLAT_NUM_IO_APICS 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEM_INIT_PSTATE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the</span><br><span style="color: hsl(120, 100%, 40%);">+ // core for C-state entry requests. A value</span><br><span style="color: hsl(120, 100%, 40%);">+ // of 0 in this field specifies that the core</span><br><span style="color: hsl(120, 100%, 40%);">+ // does not trap any IO addresses for C-state entry.</span><br><span style="color: hsl(120, 100%, 40%);">+ // Values greater than 0xFFF8 results in undefined behavior.</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_POWER_DOWN TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_ONLINE_SPARE FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_BANK_SWIZZLE TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_DQS_TRAINING_CONTROL TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_USE_BURST_MODE FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_ENABLE_ECC_FEATURE FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_ECC_REDIRECTION FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_SCRUB_DRAM_RATE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_SCRUB_L2_RATE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_SCRUB_L3_RATE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_SCRUB_IC_RATE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_SCRUB_DC_RATE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_ECC_SYNC_FLOOD FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_ECC_SYMBOL_SIZE 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_1GB_ALIGN FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_IOMMU_SUPPORT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define OPTION_GFX_INIT_SVIEW FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_CFG_ABM_SUPPORT TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef PCIEX_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Process the options...</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file include MUST occur AFTER the user option selection settings</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Customized OEM build configurations for FCH component</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_AZALIA_SSID 0x780D1022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SMBUS_SSID 0x780B1022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_IDE_SSID 0x780C1022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SATA_AHCI_SSID 0x78011022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SATA_IDE_SSID 0x78001022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SATA_RAID5_SSID 0x78031022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SATA_RAID_SSID 0x78021022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_EHCI_SSID 0x78081022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_OHCI_SSID 0x78071022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_LPC_SSID 0x780E1022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_SD_SSID 0x78061022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_XHCI_SSID 0x78121022</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { CPU_LIST_TERMINAL }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Include the files that instantiate the configuration definitions. */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cpuRegisters.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cpuFamRegisters.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cpuFamilyTranslation.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "AdvancedApi.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "heapManager.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "CreateStruct.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cpuFeatures.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "Table.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cpuEarlyInit.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cpuLateInit.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "GnbInterface.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // This is the delivery package title, "BrazosPI"</span><br><span style="color: hsl(120, 100%, 40%);">+ // This string MUST be exactly 8 characters long</span><br><span style="color: hsl(120, 100%, 40%);">+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // This is the release version number of the AGESA component</span><br><span style="color: hsl(120, 100%, 40%);">+ // This string MUST be exactly 12 characters long</span><br><span style="color: hsl(120, 100%, 40%);">+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* MEMORY_BUS_SPEED */</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR400_FREQUENCY 200 ///< DDR 400</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR533_FREQUENCY 266 ///< DDR 533</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR667_FREQUENCY 333 ///< DDR 667</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR800_FREQUENCY 400 ///< DDR 800</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR1066_FREQUENCY 533 ///< DDR 1066</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR1333_FREQUENCY 667 ///< DDR 1333</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR1600_FREQUENCY 800 ///< DDR 1600</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR1866_FREQUENCY 933 ///< DDR 1866</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR2100_FREQUENCY 1050 ///< DDR 2100</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR2133_FREQUENCY 1066 ///< DDR 2133</span><br><span style="color: hsl(120, 100%, 40%);">+//#define DDR2400_FREQUENCY 1200 ///< DDR 2400</span><br><span style="color: hsl(120, 100%, 40%);">+//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+///* QUANDRANK_TYPE*/</span><br><span style="color: hsl(120, 100%, 40%);">+//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM</span><br><span style="color: hsl(120, 100%, 40%);">+//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+///* USER_MEMORY_TIMING_MODE */</span><br><span style="color: hsl(120, 100%, 40%);">+//#define TIMING_MODE_AUTO 0 ///< Use best rate possible</span><br><span style="color: hsl(120, 100%, 40%);">+//#define TIMING_MODE_LIMITED 1 ///< Set user top limit</span><br><span style="color: hsl(120, 100%, 40%);">+//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+///* POWER_DOWN_MODE */</span><br><span style="color: hsl(120, 100%, 40%);">+//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode</span><br><span style="color: hsl(120, 100%, 40%);">+//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Agesa optional capabilities selection.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Uncomment and mark FALSE those features you wish to include in the build.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Comment out or mark TRUE those features you want to REMOVE from the build.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_HPET_BASE_ADDRESS 0xFED00000</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SMI_CMD_PORT 0xB0</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_GEC_BASE_ADDRESS 0xFED61000</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_AZALIA_SSID 0x780D1022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SMBUS_SSID 0x780B1022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_IDE_SSID 0x780C1022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SATA_AHCI_SSID 0x78011022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SATA_IDE_SSID 0x78001022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SATA_RAID5_SSID 0x78031022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SATA_RAID_SSID 0x78021022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_EHCI_SSID 0x78081022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_OHCI_SSID 0x78071022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_LPC_SSID 0x780E1022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SD_SSID 0x78061022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_XHCI_SSID 0x78121022</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_LINK_CONFIG PortA4</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_IR_PIN_CONTROL 0x33</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+GPIO_CONTROL imba180_gpio[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {183, Function1, GpioIn | GpioOutEnB | PullUpB},</span><br><span style="color: hsl(120, 100%, 40%);">+ {-1}</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// The following definitions specify the default values for various parameters in which there are</span><br><span style="color: hsl(120, 100%, 40%);">+// no clearly defined defaults to be used in the common file. The values below are based on product</span><br><span style="color: hsl(120, 100%, 40%);">+// and BKDG content, please consult the AGESA Memory team for consultation.</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SCRUB_DRAM_RATE (0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SCRUB_L2_RATE (0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SCRUB_L3_RATE (0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SCRUB_IC_RATE (0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_SCRUB_DC_RATE (0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED</span><br><span style="color: hsl(120, 100%, 40%);">+#define DFLT_VRM_SLEW_RATE (5000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <PlatformInstall.h></span><br><span>diff --git a/src/mainboard/asus/am1i-a/cmos.default b/src/mainboard/asus/am1i-a/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..dcacda6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/cmos.default</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Spew</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=IDE</span><br><span style="color: hsl(120, 100%, 40%);">+sata_speed=6Gbps</span><br><span>diff --git a/src/mainboard/asus/am1i-a/cmos.layout b/src/mainboard/asus/am1i-a/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..854ed11</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/cmos.layout</span><br><span>@@ -0,0 +1,63 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#*****************************************************************************</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#*****************************************************************************</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#start-bit length config config-ID name</span><br><span style="color: hsl(120, 100%, 40%);">+0 384 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 r 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+#400 1 e 1 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+412 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+416 4 e 7 boot_first</span><br><span style="color: hsl(120, 100%, 40%);">+420 4 e 7 boot_second</span><br><span style="color: hsl(120, 100%, 40%);">+424 4 e 7 boot_third</span><br><span style="color: hsl(120, 100%, 40%);">+428 4 r 0 boot_index</span><br><span style="color: hsl(120, 100%, 40%);">+432 8 r 0 boot_countdown</span><br><span style="color: hsl(120, 100%, 40%);">+440 8 e 10 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+448 8 e 11 sata_speed</span><br><span style="color: hsl(120, 100%, 40%);">+#728 256 h 0 user_data</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+# Reserve the extended AMD configuration registers</span><br><span style="color: hsl(120, 100%, 40%);">+1000 24 r 0 amd_reserved</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+#1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+#1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 9 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Network</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 HDD</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+7 8 Fallback_Network</span><br><span style="color: hsl(120, 100%, 40%);">+7 9 Fallback_HDD</span><br><span style="color: hsl(120, 100%, 40%);">+7 10 Fallback_Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+10 0 IDE</span><br><span style="color: hsl(120, 100%, 40%);">+10 2 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+11 1 3Gbps</span><br><span style="color: hsl(120, 100%, 40%);">+11 0 6Gbps</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 455 984</span><br><span>diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..30afd95</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/devicetree.cb</span><br><span>@@ -0,0 +1,113 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2013 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/amd/agesa/family16kb/root_complex</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/amd/agesa/family16kb</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1043 0x8623 inherit</span><br><span style="color: hsl(120, 100%, 40%);">+ chip northbridge/amd/agesa/family16kb # CPU side of HT root complex</span><br><span style="color: hsl(120, 100%, 40%);">+ chip northbridge/amd/agesa/family16kb # PCI side of HT root complex</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # Root Complex</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9804</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.1 on end # Internal Multimedia</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.1 on end # x4 PCIe slot</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.2 on end # mPCIe slot</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.3 on end # Realtek NIC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.4 on end # Edge Connector</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.5 on end # Edge Connector</span><br><span style="color: hsl(120, 100%, 40%);">+ end #chip northbridge/amd/agesa/family16kb</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 on end # XHCI HC0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/generic #dimm 0-0-0</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 50 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/generic #dimm 0-0-1</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 51 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # SM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 on end # HDA 0x4383</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.3 on # LPC 0x439d</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/ite/it8623e</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off # FDC - not used</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # COM2</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on # Parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x778</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 5</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.4 on # EC</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x230</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # PS/2 keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 on # PS/2 mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 on # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x300</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end #superio/ite/it8623e</span><br><span style="color: hsl(120, 100%, 40%);">+ end #device pci 14.3 # LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.7 on end # SD</span><br><span style="color: hsl(120, 100%, 40%);">+ end #chip southbridge/amd/agesa/hudson</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.4 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.5 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spdAddrLookup" = "</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ { {0xA0, 0xA2} },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex</span><br><span style="color: hsl(120, 100%, 40%);">+ end #domain</span><br><span style="color: hsl(120, 100%, 40%);">+end #northbridge/amd/agesa/family16kb/root_complex</span><br><span>diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..281669c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/dsdt.asl</span><br><span>@@ -0,0 +1,95 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* DefinitionBlock Statement */</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock (</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT.AML", /* Output filename */</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT", /* Signature */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ "AMD ", /* OEMID */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", /* TABLE ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00010001 /* OEM Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ )</span><br><span style="color: hsl(120, 100%, 40%);">+{ /* Start of ASL file */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Globals for the platform */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/mainboard.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe the USB Overcurrent pins */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/usb_oc.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI IRQ mapping for the Southbridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe the processor tree (\_PR) */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/amd/agesa/family16kb/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Contains the supported sleep states for this chipset */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/common/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/sleep.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* stuff for sio */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/flag0.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* System Bus */</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope(\_SB) { /* Start \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global utility methods expected within the \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <arch/x86/acpi/globutil.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/routing.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(PWRB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_HID, EISAID("PNP0C0C"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_UID, 0xAA)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_PRW, Package () {3, 0x04})</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_STA, 0x0B)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device(PCI0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe the AMD Northbridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe the AMD Fusion Controller Hub Southbridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* sio fixup */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/sio.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe PCI INT[A-H] for the Southbridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End \_SB scope */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe SMBUS for the Southbridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Define the General Purpose Events for the platform */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/gpe.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Define the Thermal zones and methods for the platform */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/thermal.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Define the System Indicators for the platform */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/si.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/* End of ASL file */</span><br><span>diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..359cc25</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/irq_tables.c</span><br><span>@@ -0,0 +1,50 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/pirq_routing.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct irq_routing_table intel_irq_routing_table = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_SIGNATURE, /* u32 signature */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_VERSION, /* u16 version */</span><br><span style="color: hsl(120, 100%, 40%);">+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, /* Interrupt router bus */</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x14 << 3) | 0x3, /* Interrupt router dev */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* IRQs devoted exclusively to PCI usage */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1002, /* Vendor */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x439d, /* Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* Miniport */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x24, /* Checksum (has to be set to some value that</span><br><span style="color: hsl(120, 100%, 40%);">+ * would give 0 after the sum of all bytes</span><br><span style="color: hsl(120, 100%, 40%);">+ * for this structure (including checksum).</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x01 << 3) | 0x0, {{0x05, 0xccb0}, {0x06, 0xccb0}, {0x07, 0xccb0}, {0x08, 0xccb0}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x02 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xccb0}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x14 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xccb0}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x12 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x13 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x16 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x10 << 3) | 0x0, {{0x03, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00, (0x11 << 3) | 0x0, {{0x04, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x01, (0x00 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xccb0}}, 0x0, 0x0},</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long write_pirq_routing_table(unsigned long addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..fc7dd1d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/mainboard.c</span><br><span>@@ -0,0 +1,112 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * All Rights Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/agesa/hudson/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/amd_pci_util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/agesa/family16kb/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* INTA# - INTH# */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Misc-nil,0,1,2, INT from Serial irq */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, // HDA was 1F - now 03</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IMC INT0 - 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB Devs 18/19/22 INTA-C */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SATA & MISSING IDE */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x40] = 0x04, 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* INTA# - INTH# */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Misc-nil,0,1,2, INT from Serial irq */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x1F,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IMC INT0 - 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB Devs 18/19/20/22 INTA-C */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SATA & MISSING IDE*/</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x40] = 0x11, 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This table defines the index into the picr/intr_data</span><br><span style="color: hsl(120, 100%, 40%);">+ * tables for each device. Any enabled device and slot</span><br><span style="color: hsl(120, 100%, 40%);">+ * that uses hardware interrupts should have an entry</span><br><span style="color: hsl(120, 100%, 40%);">+ * in this table to define its index into the FCH</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCI_INTR register 0xC00/0xC01. This index will define</span><br><span style="color: hsl(120, 100%, 40%);">+ * the interrupt that it should use. Putting PIRQ_A into</span><br><span style="color: hsl(120, 100%, 40%);">+ * the PIN A index for a device will tell that device to</span><br><span style="color: hsl(120, 100%, 40%);">+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pirq_struct mainboard_pirq_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */</span><br><span style="color: hsl(120, 100%, 40%);">+ {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {LPC_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC }}, /* LPC: 14.3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u8 *picr_data = mainboard_picr_data;</span><br><span style="color: hsl(120, 100%, 40%);">+const u8 *intr_data = mainboard_intr_data;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PIRQ Setup */</span><br><span style="color: hsl(120, 100%, 40%);">+static void pirq_setup(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_data_ptr = mainboard_pirq_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);</span><br><span style="color: hsl(120, 100%, 40%);">+ intr_data_ptr = mainboard_intr_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ picr_data_ptr = mainboard_picr_data;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**********************************************</span><br><span style="color: hsl(120, 100%, 40%);">+ * enable the dedicated function in mainboard.</span><br><span style="color: hsl(120, 100%, 40%);">+ **********************************************/</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the PIRQ data structures for consumption */</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_setup();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3866f2e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/mptable.c</span><br><span>@@ -0,0 +1,164 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/amd_pci_util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/generic/ioapic/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void *smp_write_config_table(void *v)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct mp_config_table *mc;</span><br><span style="color: hsl(120, 100%, 40%);">+ int bus_isa;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * By the time this function gets called, the IOAPIC registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * have been written so they can be read to get the correct</span><br><span style="color: hsl(120, 100%, 40%);">+ * APIC ID and Version</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 0: Processor Entries:</span><br><span style="color: hsl(120, 100%, 40%);">+ * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPU Signature (Stepping, Model, Family),</span><br><span style="color: hsl(120, 100%, 40%);">+ * Feature Flags</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_processors(mc);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 1: Bus Entries:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bus ID, Bus Type</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_write_buses(mc, NULL, &bus_isa);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 2: I/O APICs:</span><br><span style="color: hsl(120, 100%, 40%);">+ * APIC ID, Version, APIC Flags:EN, Address</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 3: I/O Interrupt Table Entries:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Int Type, Int Polarity, Int Level, Source Bus ID,</span><br><span style="color: hsl(120, 100%, 40%);">+ * Source Bus IRQ, Dest APIC ID, Dest PIN#</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI interrupts are level triggered, and are</span><br><span style="color: hsl(120, 100%, 40%);">+ * associated with a specific bus/device/function tuple.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_INT(bus, dev, fn, pin) \</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* APU Internal Graphic Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SMBUS / ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Southbridge HD Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* on board NIC & Slot PCIE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI slots */</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev && dev->enabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 bus_pci = dev->link_list->secondary;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI_SLOT 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI_SLOT 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI_SLOT 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe Lan*/</span><br><span style="color: hsl(120, 100%, 40%);">+ //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FCH PCIe PortA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FCH PCIe PortB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FCH PCIe PortC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FCH PCIe PortD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IO_LOCAL_INT(type, intr, apicid, pin) \</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* There is no extension information... */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Compute the checksums */</span><br><span style="color: hsl(120, 100%, 40%);">+ return mptable_finalize(mc);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long write_smp_table(unsigned long addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ void *v;</span><br><span style="color: hsl(120, 100%, 40%);">+ v = smp_write_floating_table(addr, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ return (unsigned long)smp_write_config_table(v);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..baac29a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/am1i-a/romstage.c</span><br><span>@@ -0,0 +1,173 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/loglevel.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/agesa/state_machine.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/amd_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/agesa/hudson/hudson.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/common/ite.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/it8623e/it8623e.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ITE_CONFIG_REG_CC 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_DEV PNP_DEV(0x2e, IT8623E_GPIO)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CLKIN_DEV PNP_DEV(0x2e, IT8623E_GPIO)</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENVC_DEV PNP_DEV(0x2e, IT8623E_EC)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Sets up EC configuration as per vendor defaults */</span><br><span style="color: hsl(120, 100%, 40%);">+static void ite_evc_conf(pnp_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_set_enable(dev, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x70 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf0 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf1 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf2 , 0x06 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf3 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf4 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf5 , 0x36 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf6 , 0x03 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf9 , 0x48 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xfa , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xfb , 0x10 );</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_set_enable(dev, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Sets up GPIO configuration as per vendor defaults */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SIO defaults are unknown therefore all GPIO pins are configured */</span><br><span style="color: hsl(120, 100%, 40%);">+static void ite_gpio_conf(pnp_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x23 , 0x08 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x25 , 0x10 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x26 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x27 , 0x80 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x28 , 0x45 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x29 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x2a , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x2b , 0x48 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x2c , 0x10 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x2d , 0x80 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x71 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x72 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x73 , 0x38 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0x74 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xb0 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xb1 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xb2 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xb3 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xb4 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xb8 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xb9 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xba , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xbb , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xbc , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xbd , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xc0 , 0x01 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xc1 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xc2 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xc3 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xc4 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xc8 , 0x01 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xc9 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xca , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xcb , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xcc , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xcd , 0x20 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xce , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xcf , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xe0 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xe1 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xe2 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xe3 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xe4 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xe9 , 0x21 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf0 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf1 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf2 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf3 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf4 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf5 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf6 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf7 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf8 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xf9 , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xfa , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_reg_write(dev, 0xfb , 0x00 );</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void board_BeforeAgesa(struct sysinfo *cb)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 t32, val;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 byte;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *addr32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for</span><br><span style="color: hsl(120, 100%, 40%);">+ * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA</span><br><span style="color: hsl(120, 100%, 40%);">+ * even though the register is not documented in the Kabini BKDG.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Otherwise the serial output is bad code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0xD2, 0xcd6);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x00, 0xcd7);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0xEA, 0xcd6);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x1, 0xcd7);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set LPC decode enables. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev2, 0x44, 0xff03ffd5);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hudson_lpc_port80();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable the AcpiMmio space */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x24, 0xcd6);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x1, 0xcd7);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure ClkDrvStr1 settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ addr32 = (u32 *)0xfed80e24;</span><br><span style="color: hsl(120, 100%, 40%);">+ t32 = *addr32;</span><br><span style="color: hsl(120, 100%, 40%);">+ t32 = 0x030800aa;</span><br><span style="color: hsl(120, 100%, 40%);">+ *addr32 = t32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure MiscClkCntl1 settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ addr32 = (u32 *)0xfed80e40;</span><br><span style="color: hsl(120, 100%, 40%);">+ t32 = *addr32;</span><br><span style="color: hsl(120, 100%, 40%);">+ t32 = 0x000c4050;</span><br><span style="color: hsl(120, 100%, 40%);">+ *addr32 = t32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable SIO LPC decode */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = PCI_DEV(0, 0x14, 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = pci_read_config8(dev, 0x48);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= 3; /* 2e, 2f & 4e, 4f */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, 0x48, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_gpio_conf(GPIO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_evc_conf(ENVC_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_kill_watchdog(GPIO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 200000; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ val = inb(0xcd6);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23002">change 23002</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23002"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7 </div>
<div style="display:none"> Gerrit-Change-Number: 23002 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Gergely Kiss <mail.gery@gmail.com> </div>