<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22986">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/southbridge.c: Create a GPIO programming function<br><br>Create a GPIO programming function that can be called from multiple stages<br>(bootblock, romstage and ramstage) that will program only the GPIO specific<br>to the particular stage.<br><br>Add dummy table to kahlee to be able to test a build.<br><br>BUG=b:64140392<br>TEST=Build kahlee.<br><br>Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>M src/mainboard/google/kahlee/variants/kahlee/gpio.c<br>M src/soc/amd/stoneyridge/include/soc/iomap.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>5 files changed, 112 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/22986/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>index 250fcc1..35b35d1 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>@@ -21,6 +21,30 @@</span><br><span> #include <stdlib.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The definitions bellow are valid only within this file, with the sole</span><br><span style="color: hsl(120, 100%, 40%);">+ * purpose of making the array below compact and easy to understand.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PULL_UP FCH_GPIO_PULL_UP_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INPUT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define OUTPUT_H (FCH_GPIO_OUTPUT_ENABLE | FCH_GPIO_OUTPUT_VALUE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define OUTPUT_L FCH_GPIO_OUTPUT_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * These settings were generated by a spreadsheet. If they need to be updated,</span><br><span style="color: hsl(120, 100%, 40%);">+ * update the spreadsheet shared with the Grunt development team.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * As a rule of thumb, GPIO used by coreboot should be initialized at</span><br><span style="color: hsl(120, 100%, 40%);">+ * STAGE_RESET while GPIO used only by the OS should be initialized at</span><br><span style="color: hsl(120, 100%, 40%);">+ * STAGE_INIT_LATE.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_stoneyridge_gpio gpio_set_stage[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_0 - EC_PCH_PWR_BTN_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPIO_0, Function0, PULL_UP | INPUT, STAGE_RESET }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span> * These settings were generated by a spreadsheet. If they need to be updated,</span><br><span> * update the spreadsheet shared with the Grunt development team.</span><br><span> */</span><br><span>@@ -260,6 +284,14 @@</span><br><span> return agesa_board_gpios;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+const __attribute__((weak)) const struct</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * GPE setup table must match ACPI GPE ASL</span><br><span> * { gevent, gpe, direction, level }</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>index e5e15e6..8d76ee9 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c</span><br><span>@@ -20,6 +20,26 @@</span><br><span> #include <stdlib.h></span><br><span> #include <variant/gpio.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The definitions bellow are valid only within this file, with the sole</span><br><span style="color: hsl(120, 100%, 40%);">+ * purpose of making the array below compact and easy to understand.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PULL_UP FCH_GPIO_PULL_UP_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define INPUT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define OUTPUT_H (FCH_GPIO_OUTPUT_ENABLE | FCH_GPIO_OUTPUT_VALUE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define OUTPUT_L FCH_GPIO_OUTPUT_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * As a rule of thumb, GPIO used by coreboot should be initialized at</span><br><span style="color: hsl(120, 100%, 40%);">+ * STAGE_RESET while GPIO used only by the OS should be initialized at</span><br><span style="color: hsl(120, 100%, 40%);">+ * STAGE_INIT_LATE.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio gpio_set_stage[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* AGPIO2, to become event generator */</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPIO_2, Function1, PULL_UP | INPUT, STAGE_RESET }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const GPIO_CONTROL agesa_board_gpios[] = {</span><br><span> /* AGPIO2 PCIE/WLAN WAKE# SCI*/</span><br><span> {2, Function1, FCH_GPIO_PULL_UP_ENABLE },</span><br><span>@@ -104,6 +124,12 @@</span><br><span> return agesa_board_gpios;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * GPE setup table must match ACPI GPE ASL</span><br><span> * { gevent, gpe, direction, level }</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>index 64a9b30..9df1e6b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>@@ -50,4 +50,8 @@</span><br><span> #define AB_DATA (AB_INDX+4)</span><br><span> #define SYS_RESET 0xcf9</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO control and mux access */</span><br><span style="color: hsl(120, 100%, 40%);">+#define AMD_GPIO_MUX (AMD_SB_ACPI_MMIO_ADDR + 0x00000d00)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AMD_GPIO_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x00001500)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* __SOC_STONEYRIDGE_IOMAP_H__ */</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index bbf6344..1d03822 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -271,7 +271,6 @@</span><br><span> #define XHCI_PM_INDIRECT_INDEX 0x48</span><br><span> #define XHCI_PM_INDIRECT_DATA 0x4C</span><br><span> #define XHCI_OVER_CURRENT_CONTROL 0x30</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define EHCI_OVER_CURRENT_CONTROL 0x70</span><br><span> </span><br><span> #define USB_OC0 0</span><br><span>@@ -293,6 +292,18 @@</span><br><span> #define WIDEIO_RANGE_ERROR -1</span><br><span> #define TOTAL_WIDEIO_PORTS 3</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_CONTROL_MASK 0x00f00000</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_UNKNOWN_BIT 0x00040000 /* cleared by AGESA */</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_stoneyridge_gpio {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t function;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t control;</span><br><span style="color: hsl(120, 100%, 40%);">+ enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ STAGE_RESET,</span><br><span style="color: hsl(120, 100%, 40%);">+ STAGE_INIT_LATE</span><br><span style="color: hsl(120, 100%, 40%);">+ } stage;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static inline int sb_sata_enable(void)</span><br><span> {</span><br><span> /* True if IDE or AHCI. */</span><br><span>@@ -346,6 +357,8 @@</span><br><span> int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);</span><br><span> int s3_save_nvram_early(u32 dword, int size, int nvram_pos);</span><br><span> void bootblock_fch_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_program_gpio(int stage);</span><br><span> /**</span><br><span> * @brief Find the size of a particular wide IO</span><br><span> *</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 1357257..77a424b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -142,6 +142,42 @@</span><br><span> return irq_association;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void sb_program_gpio(int stage)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t *control_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *mux_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_stoneyridge_gpio *gpio_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ptr_build, control_value;</span><br><span style="color: hsl(120, 100%, 40%);">+ int gpio = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t size;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t control, mux, index;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GPIO programming stage %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ (stage == STAGE_RESET) ? "reset" : "init late");</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_ptr = board_get_gpio(&size);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (index = 0; index < size; index++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio_ptr[index].stage == stage) {</span><br><span style="color: hsl(120, 100%, 40%);">+ mux = gpio_ptr[index].function;</span><br><span style="color: hsl(120, 100%, 40%);">+ control = gpio_ptr[index].control;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio = gpio_ptr[index].gpio;</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_ptr = (uint8_t *) gpio + AMD_GPIO_MUX;</span><br><span style="color: hsl(120, 100%, 40%);">+ *mux_ptr = (mux & 0x03); /* clear reserved bits */</span><br><span style="color: hsl(120, 100%, 40%);">+ ptr_build = gpio * 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ ptr_build += AMD_GPIO_CONTROL;</span><br><span style="color: hsl(120, 100%, 40%);">+ control_ptr = (uint32_t *)ptr_build;</span><br><span style="color: hsl(120, 100%, 40%);">+ control_value = *control_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ control_value &= ~(GPIO_CONTROL_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_UNKNOWN_BIT);</span><br><span style="color: hsl(120, 100%, 40%);">+ control_value |= ((control << 16) & GPIO_CONTROL_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ *control_ptr = control_value;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GPIO%-3d function%d set to"</span><br><span style="color: hsl(120, 100%, 40%);">+ " 0x%08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio, mux, *control_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "End GPIO programming\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /**</span><br><span> * @brief Find the size of a particular wide IO</span><br><span> *</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22986">change 22986</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22986"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 </div>
<div style="display:none"> Gerrit-Change-Number: 22986 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>