<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22993">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x/raminit: Support programming initials DD3 DLL setting<br><br>Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/x4x/raminit_ddr23.c<br>1 file changed, 205 insertions(+), 59 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/22993/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>index 5ad4453..a4b11d5 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>@@ -583,7 +583,8 @@</span><br><span> MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) |</span><br><span> s->selected_timings.tRFC;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) | (100 << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe)</span><br><span style="color: hsl(120, 100%, 40%);">+ | ((s->spd_type == DDR2 ? 100 : 256) << 1);</span><br><span> MCHBAR8(0x400*i + 0x264) = 0xff;</span><br><span> MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) |</span><br><span> s->selected_timings.tRAS;</span><br><span>@@ -636,18 +637,32 @@</span><br><span> MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3;</span><br><span> </span><br><span> reg16 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- switch (s->selected_timings.mem_clk) {</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- case MEM_CLOCK_667MHz:</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = 0x99;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case MEM_CLOCK_800MHz:</span><br><span style="color: hsl(0, 100%, 40%);">- if (s->selected_timings.CAS == 5)</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = 0x19a;</span><br><span style="color: hsl(0, 100%, 40%);">- else if (s->selected_timings.CAS == 6)</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = 0x9a;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->spd_type == DDR2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (s->selected_timings.mem_clk) {</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_667MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = 0x99;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_800MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.CAS == 5)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = 0x19a;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (s->selected_timings.CAS == 6)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = 0x9a;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } else { /* DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (s->selected_timings.mem_clk) {</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_800MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1066MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1333MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> reg16 &= 0x7;</span><br><span> reg16 += twl + 9;</span><br><span> reg16 <<= 10;</span><br><span>@@ -683,6 +698,13 @@</span><br><span> MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8;</span><br><span> MCHBAR8(0x12f) = 0x4c;</span><br><span> reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->spd_type == DDR3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x114) = 0x42;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = (512 - MAX(5, s->selected_timings.tRFC +</span><br><span style="color: hsl(120, 100%, 40%);">+ 10000 / ddr2ps[s->selected_timings.mem_clk])) / 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 &= 0x1ff;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32;</span><br><span> MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2;</span><br><span> }</span><br><span>@@ -693,6 +715,9 @@</span><br><span> u16 reg16 = 0;</span><br><span> u32 reg32 = 0;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x08, 0x10 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04;</span><br><span> MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8;</span><br><span> MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f;</span><br><span>@@ -701,11 +726,15 @@</span><br><span> switch (s->selected_timings.mem_clk) {</span><br><span> default:</span><br><span> case MEM_CLOCK_667MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1333MHz:</span><br><span> reg16 = (0xa << 9) | 0xa;</span><br><span> break;</span><br><span> case MEM_CLOCK_800MHz:</span><br><span> reg16 = (0x9 << 9) | 0x9;</span><br><span> break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1066MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = (0x7 << 9) | 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span> }</span><br><span> MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16;</span><br><span> MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010;</span><br><span>@@ -729,14 +758,26 @@</span><br><span> udelay(1); // 533ns</span><br><span> </span><br><span> // ME related</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) | 0x551803;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->spd_type == DDR2 ? 0x551803 : 0x555801);</span><br><span> </span><br><span> MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->spd_type == DDR2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else { /* DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = 0x9; /* 0x9 << 4 ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->dimms[0].ranks == 2)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 &= ~0x80;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->dimms[3].ranks == 2)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 &= ~0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x1a8) = (MCHBAR8(0x1a8) & ~0xf0) | reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> FOR_EACH_CHANNEL(i) {</span><br><span> reg16 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x59c) = MCHBAR16(0x400*i + 0x59c) & ~0x3000;</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((s->spd_type == DDR3) && (i == 0))</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = (0x3 << 12);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16(0x400*i + 0x59c) = (MCHBAR16(0x400*i + 0x59c) & ~0x3000) | reg16;</span><br><span> </span><br><span> reg32 = 0;</span><br><span> FOR_EACH_RANK_IN_CHANNEL(r) {</span><br><span>@@ -747,30 +788,49 @@</span><br><span> MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32;</span><br><span> MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (!CHANNEL_IS_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "No dimms in channel %d\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = 0x3f;</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = 0x38;</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = 0x7;</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- die("Unhandled case\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->spd_type == DDR2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!CHANNEL_IS_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "No dimms in channel %d\n", i);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = 0x3f;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "DimmA populated only in channel %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ i);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = 0x38;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "DimmB populated only in channel %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ i);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "Both dimms populated in channel %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ i);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Unhandled case\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0)</span><br><span style="color: hsl(120, 100%, 40%);">+ & ~0x3f000000) | ((u32)(reg8 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } else { /* DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x400 * i + 0x5a0 + 3) = MCHBAR8(0x400 * i + 0x5a0 + 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ & ~rank2clken[r + i * 4];</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> //reg8 = 0x00; // FIXME don't switch on all clocks anyway</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) |</span><br><span style="color: hsl(0, 100%, 40%);">- ((u32)(reg8 << 24));</span><br><span> } // END EACH CHANNEL</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->spd_type == DDR2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else { /* DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> // Update DLL timing</span><br><span> MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80;</span><br><span>@@ -780,12 +840,16 @@</span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {</span><br><span> MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc;</span><br><span> MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) | 0x70;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) | 0x5555;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->spd_type == DDR2 ? 0x70 : 0x60);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (s->spd_type == DDR2 ? 0x5555 : 0xa955);</span><br><span> }</span><br><span> </span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch(s->selected_timings.mem_clk) {</span><br><span style="color: hsl(120, 100%, 40%);">+ default: /* Should not happen */</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_667MHz:</span><br><span> clkset0(i, &default_ddr2_667_ctrl[CLKSET0]);</span><br><span> clkset1(i, &default_ddr2_667_ctrl[CLKSET1]);</span><br><span> ctrlset0(i, &default_ddr2_667_ctrl[CTRL0]);</span><br><span>@@ -793,14 +857,65 @@</span><br><span> ctrlset2(i, &default_ddr2_667_ctrl[CTRL2]);</span><br><span> ctrlset3(i, &default_ddr2_667_ctrl[CTRL3]);</span><br><span> cmdset(i, &default_ddr2_667_ctrl[CMD]);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- clkset0(i, &default_ddr2_800_ctrl[CLKSET0]);</span><br><span style="color: hsl(0, 100%, 40%);">- clkset1(i, &default_ddr2_800_ctrl[CLKSET1]);</span><br><span style="color: hsl(0, 100%, 40%);">- ctrlset0(i, &default_ddr2_800_ctrl[CTRL0]);</span><br><span style="color: hsl(0, 100%, 40%);">- ctrlset1(i, &default_ddr2_800_ctrl[CTRL1]);</span><br><span style="color: hsl(0, 100%, 40%);">- ctrlset2(i, &default_ddr2_800_ctrl[CTRL2]);</span><br><span style="color: hsl(0, 100%, 40%);">- ctrlset3(i, &default_ddr2_800_ctrl[CTRL3]);</span><br><span style="color: hsl(0, 100%, 40%);">- cmdset(i, &default_ddr2_800_ctrl[CMD]);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_800MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->spd_type == DDR2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset0(i, &default_ddr2_800_ctrl[CLKSET0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset1(i, &default_ddr2_800_ctrl[CLKSET1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset0(i, &default_ddr2_800_ctrl[CTRL0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset1(i, &default_ddr2_800_ctrl[CTRL1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset2(i, &default_ddr2_800_ctrl[CTRL2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset3(i, &default_ddr2_800_ctrl[CTRL3]);</span><br><span style="color: hsl(120, 100%, 40%);">+ cmdset(i, &default_ddr2_800_ctrl[CMD]);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else { /* DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset0(i, &default_ddr3_800_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CLKSET0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset1(i, &default_ddr3_800_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CLKSET1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset0(i, &default_ddr3_800_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset1(i, &default_ddr3_800_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset2(i, &default_ddr3_800_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset3(i, &default_ddr3_800_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL3]);</span><br><span style="color: hsl(120, 100%, 40%);">+ cmdset(i, &default_ddr3_800_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CMD]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1066MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset0(i, &default_ddr3_1067_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CLKSET0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset1(i, &default_ddr3_1067_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CLKSET1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset0(i, &default_ddr3_1067_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset1(i, &default_ddr3_1067_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset2(i, &default_ddr3_1067_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset3(i, &default_ddr3_1067_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL3]);</span><br><span style="color: hsl(120, 100%, 40%);">+ cmdset(i, &default_ddr3_1067_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CMD]);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1333MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset0(i, &default_ddr3_1333_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CLKSET0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ clkset1(i, &default_ddr3_1333_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CLKSET1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset0(i, &default_ddr3_1333_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset1(i, &default_ddr3_1333_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset2(i, &default_ddr3_1333_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL2]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlset3(i, &default_ddr3_1333_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CTRL3]);</span><br><span style="color: hsl(120, 100%, 40%);">+ cmdset(i, &default_ddr3_1333_ctrl[s->nmode - 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ [CMD]);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -867,23 +982,39 @@</span><br><span> }</span><br><span> </span><br><span> clk = 0x1a;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ clk = 0x18;</span><br><span> if (async != 1) {</span><br><span> reg8 = MCHBAR8(0x188) & 0x1e;</span><br><span style="color: hsl(0, 100%, 40%);">- if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz &&</span><br><span style="color: hsl(0, 100%, 40%);">- s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) {</span><br><span style="color: hsl(0, 100%, 40%);">- clk = 0x10;</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) {</span><br><span style="color: hsl(0, 100%, 40%);">- clk = 0x10;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (s->selected_timings.mem_clk) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_667MHz:</span><br><span> clk = 0x1a;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ clk = 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_800MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1066MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ clk = 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_CLOCK_1333MHz:</span><br><span style="color: hsl(120, 100%, 40%);">+ clk = 0x18;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ clk = 0x1a;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) &&</span><br><span style="color: hsl(0, 100%, 40%);">- (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz</span><br><span style="color: hsl(120, 100%, 40%);">+ && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {</span><br><span> i = MCHBAR8(0x1c8) & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- i = (i + 10) % 14;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s->spd_type == DDR2)</span><br><span style="color: hsl(120, 100%, 40%);">+ i = (i + 10) % 14;</span><br><span style="color: hsl(120, 100%, 40%);">+ else /* DDR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ i = (i + 3) % 12;</span><br><span> MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;</span><br><span> MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;</span><br><span> while (MCHBAR8(0x180) & 0x10)</span><br><span>@@ -929,18 +1060,33 @@</span><br><span> s->rt_dqs[ch][lane].tap = 7;</span><br><span> s->rt_dqs[ch][lane].pi = 0;</span><br><span> } else { /* DDR3 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO: DDR3 write DQ-DQS */</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(s->dqs_settings[ch],</span><br><span style="color: hsl(120, 100%, 40%);">+ default_ddr3_800_dqs[s->nmode - 1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(s->dqs_settings[ch]));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(s->dq_settings[ch],</span><br><span style="color: hsl(120, 100%, 40%);">+ default_ddr3_800_dq[s->nmode - 1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(s->dq_settings[ch]));</span><br><span> s->rt_dqs[ch][lane].tap = 6;</span><br><span style="color: hsl(0, 100%, 40%);">- s->rt_dqs[ch][lane].pi = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ s->rt_dqs[ch][lane].pi = 3;</span><br><span> }</span><br><span> break;</span><br><span> case MEM_CLOCK_1066MHz:</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO: DDR3 write DQ-DQS */</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(s->dqs_settings[ch],</span><br><span style="color: hsl(120, 100%, 40%);">+ default_ddr3_1067_dqs[s->nmode - 1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(s->dqs_settings[ch]));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(s->dq_settings[ch],</span><br><span style="color: hsl(120, 100%, 40%);">+ default_ddr3_1067_dq[s->nmode - 1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(s->dq_settings[ch]));</span><br><span> s->rt_dqs[ch][lane].tap = 5;</span><br><span style="color: hsl(0, 100%, 40%);">- s->rt_dqs[ch][lane].pi = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ s->rt_dqs[ch][lane].pi = 3;</span><br><span> break;</span><br><span> case MEM_CLOCK_1333MHz:</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO: DDR3 write DQ-DQS */</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(s->dqs_settings[ch],</span><br><span style="color: hsl(120, 100%, 40%);">+ default_ddr3_1333_dqs[s->nmode - 1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(s->dqs_settings[ch]));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(s->dq_settings[ch],</span><br><span style="color: hsl(120, 100%, 40%);">+ default_ddr3_1333_dq[s->nmode - 1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(s->dq_settings[ch]));</span><br><span> s->rt_dqs[ch][lane].tap = 7;</span><br><span> s->rt_dqs[ch][lane].pi = 0;</span><br><span> break;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22993">change 22993</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22993"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 </div>
<div style="display:none"> Gerrit-Change-Number: 22993 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>